參數(shù)資料
型號(hào)： M32182F3VFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù)： 20/36頁
文件大?。?/td> 292K
代理商： M32182F3VFP
2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group
Under Development
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
27
SCLKI0/ SCLKO0
BCLK,
BCLK/8,
BCLK/32,
BCLK/256
Baud rate
generator
(BRG)
BCLK
(Set value + 1)
1
Inter
nal
data
bus
CSIO mode
When internal clock selected
CSIO
mode
UART
mode
When internal clock selected
1/16
1/2
RXD0
TXD0
Receive interrupt
Transmit
/receive
control
circuit
Receive DMA transfer request
Transmit interrupt
Transmit DMA transfer request
To DMAC 3,DMAC4
SIO0 Receive Buffer Register
When external clock selected
When UART mode selected
Note2: SIO2 and SIO3 do not have the SCLKI/SCLKO function.
Note1: When BCLK is selected for the BRG count source,the BRG set value is subject to limitations.
SCLKI1/ SCLKO1
To DMAC6
To interrupt
controller
To interrupt
controller
SIO0
SIO1
SIO2
SIO3
RXD1
TXD1
SIO1 Transmit Shift Register
SIO1 Receive Shift Register
To DMAC7
RXD2
TXD2
SIO2 Transmit Shift Register
SIO2 Receive Shift Register
To DMAC9,DMA7
RXD3
TXD3
SIO3 Transmit Shift Register
SIO3 Receive Shift Register
Receive interrupt
Receive DMA transfer request
Transmit interrupt
Transmit DMA transfer request
Receive interrupt
Receive DMA transfer request
Transmit interrupt
Transmit DMA transfer request
To interrupt
controller
To DMAC8
To DMAC5
To DMAC3,DMAC6
To DMAC4
SIO0 Transmit Buffer Register
SIO0 Transmit Shift Register
SIO0 Receive Shift Register
Clock
divider
Transmit
/receive
control
circuit
Transmit
/receive
control
circuit
Transmit
/receive
control
circuit
Figure 16. Block Diagram of Serial I/O
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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