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OVERVIEW
32176 Group User’s Manual (Rev.1.01)
1.1 Outline of the 32176 Group
1.1.1 M32R Family CPU Core
(1) Based on a RISC architecture
The 32176 is a 32-bit RISC single-chip microcomputer which is built around the M32R family CPU core
(hereinafter referred to as the M32R) and incorporates flash memory, RAM and various other peripheral
functions-all integrated into a single chip.
The M32R is based on a RISC architecture. Memory is accessed using load/store instructions, and
various arithmetic operations are executed using register-to-register operation instructions. The
M32R internally contains sixteen 32-bit general-purpose registers and has 83 instructions.
The M32R supports compound instructions such as Load & Address Update and Store & Address
Update, in addition to ordinary load and store instructions. These instructions help to speed up data
transfers.
(2) Five-stage pipelined processing
The M32R supports five-stage pipelined instruction processing consisting of Instruction Fetch, De-
code, Execute, Memory Access and Write Back. Not just load/store instructions and register-to-reg-
ister operation instructions, compound instructions such as Load & Address Update and Store &
Address Update are executed in one CPUCLK period (which is equivalent to 25 ns when f(CPUCLK)
= 40 MHz).
Although instructions are supplied to the execution stage in the order in which they were fetched, it is
possible that if the load/store instruction supplied first is extended by wait cycles inserted in memory
access, the subsequent register-to-register operation instruction will be executed before that instruc-
tion. Using such a facility, which is known as the “out-of-order-completion” mechanism, the M32R is
able to control instruction execution without wasting clock cycles.
(3) Compact instruction code
The M32R supports two instruction formats: one 16 bits long, and one 32 bits long. Use of the 16-bit
instruction format especially helps to suppress the code size of a program.
Moreover, the availability of 32-bit instructions makes programming easier and provides higher per-
formance at the same clock speed than in architectures where the address space is segmented. For
example, some 32-bit instructions allow control to jump to an address 32 Mbytes forward or backward
from the currently executed address in one instruction, making programming easy.
1.1.2 Built-in Multiplier/Accumulator
(1) Built-in high-speed multiplier
The M32R contains a 32 bits × 16 bits high-speed multiplier which enables the M32R to execute a 32
bits × 32 bits integral multiplication instruction in three CPUCLK periods.
(2) DSP-comparable multiply-accumulate instructions
The M32R supports the following four types of multiply-accumulate instructions (or multiplication instruc-
tions) which each can be executed in one CPUCLK period using a 56-bit accumulator.
(1) 16 high-order bits of register × 16 high-order bits of register
(2) 16 low-order bits of register × 16 low-order bits of register
(3) Whole 32 bits of register × 16 high-order bits of register
(4) Whole 32 bits of register × 16 low-order bits of register
The M32R has some special instructions to round the value stored in the accumulator to 16 or 32 bits
or shift the accumulator value before storing in a register to have its digits adjusted. Because these
instructions are also executed in one CPUCLK period, when used in combination with high-speed
data transfer instructions such as Load & Address Update or Store & Address Update, they enable
the M32R to exhibit data processing capability comparable to that of a DSP.
1.1 Outline of the 32176 Group