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1-7
OVERVIEW
32176 Group User’s Manual (Rev.1.01)
Table 1.2.1 Features of the 32176 (2/2)
1.2 Block Diagram
Functional Block
Features
A-D converter (ADC)
16 channels: 10-bit resolution A-D converter
Conversion modes: Ordinary conversion modes plus comparator mode
Operation modes: Single conversion mode and n-channel scan mode (n = 1–16)
Sample-and-hold function: Sample-and-hold function can be enabled or disabled as necessary.
A-D disconnection detection assist function: Influences of the analog input voltage leakage from
any preceding channel during scan mode operation are suppressed.
An inflow current bypass circuit is built-in.
Can generate an interrupt or start DMA transfer upon completion of A-D conversion.
Either 8 or 10-bit conversion results can be read out.
Interrupt request: Completion of A-D conversion
DMA transfer request: Completion of A-D conversion
Serial I/O (SIO)
4-channel serial I/O
Can be chosen to be clock-synchronized serial I/O or UART.
Data can be transferred at high speed (2 Mbits per second during clock-synchronized mode or
156 Kbits per second during UART mode when f(BCLK) = 20 MHz).
Interrupt request: Reception completed, receive error, transmit buffer empty or transmission completed
DMA transfer request: Reception completed or transmit buffer empty
CAN
16 message slots × 2 blocks
Compliant with CAN specification 2.0B active.
Interrupt request: Transmission completed, reception completed, bus error, error-passive, bus-off
or single shot
DMA transfer request: Transmission failed, transmission completed or reception completed
Real-Time Debugger
Internal RAM can be rewritten or monitored independently of the CPU by entering a command
(RTD)
from the outside.
Comes with exclusive clock-synchronized serial ports.
Interrupt request: RTD interrupt command input
Interrupt Controller (ICU)
Controls interrupt requests from the internal peripheral I/O.
Supports 8-level interrupt priority including an interrupt disabled state.
External interrupt: 11 sources (SBI#, TIN0,TIN3, TIN16-TIN23)
TIN pin input sensing: Rising, falling or both edges or high or low level
Wait Controller
Controls wait states for access to the external extention area.
Insertion of 1-4 wait states by setting up in software + wait state extension by entering WAIT# signal
PLL
A multiply-by-4 clock generating circuit
Clock
Maximum external input clock frequency (XIN) is 10.0 MHz. (Note 1)
CPUCLK: Operating clock for the M32R-CPU core, internal flash memory and internal RAM
The maximum CPU clock is 40 MHz (when f(XIN) = 10 MHz).
BCLK: Operating clock for the internal peripheral I/O and external data bus
The maximum peripheral clock is 20 MHz (peripheral module access when
f(XIN) = 10 MHz).
Clock output (BCLK pin output): A clock with the same frequency as BCLK is output from this pin.
JTAG
Boundary scan function
VDC
Internal power supply generating circuit: Generates the internal power supply (2.5 V) from an
external single power supply (5 or 3.3 V).
Ports
Input/output pins: 96 pins
The port input threshold can be set in a program to one of three levels individually for each port
group (with or without Schmitt circuit, selectable).
Note 1: Maximum external input clock frequency (XIN) for the M32176F2VFP, M32176F3VFP and M32176F4VFP is 8.0 MHz.