
15
15-8
32170/32174 Group User's Manual (Rev. 2.1)
EXTERNAL BUS INTERFACE
15.2 Read/Write Operations
Figure 15.2.3 Read/Write Timing (for Access with 2 Internal and 1 External Wait Cycles)
Note: Circles
above indicate points at which signals are sampled.
"H"
(Don’t Care)
"H"
"L"
"H"
(Don’t Care)
"L"
"H"
1 external
wait cycle
2 internal wait cycles
Read (4 cycles)
BCLK
A11 - A30
CS0, CS1
BHW, BLW
DB0 - DB15
WAIT
RD
Read
Write (4 cycles)
BCLK
A11 - A30
CS0, CS1
BHW, BLW
DB0 - DB15
WAIT
RD
Write
1 external
wait cycle
2 internal wait cycles