
10
10-198
32170/32174 Group User's Manual (Rev. 2.1)
MULTIJUNCTION TIMERS
10.8 TOD (Output-related 16-bit Timer)
Figure 10.8.10 Reload 0 and Reload 1 Register Updates in PWM Output Mode
H’0001
H’FFFF
H’1000
H’7FFF
H’2000
H’8000
H’9000
H’1000
H’2000
H’8000
H’9000
H’7FFE
H’0000
H’2000
H’9000
(a) When reload register updates take effect in the current period (reflected in the next period)
Note: This diagram does not show detail timing information.
Count clock
Reload 0 register
Reload 1 register
Counter
Interrupt
by underflow
Timing at which reload 1
and reload 0 registers are updated
New PWM output period
Operation by new reload value written
Reload 0 register
Reload 1 register
F/F output
Write to reload 1
Write to reload 0
(reload 1 data latched)
Enlarged view
New PWM
output period
Old PWM output period
F/F output
PWM period latched
Reload 1 buffer
H’0001
H’FFFF
H’1000
H’0FFF
H’2000
H’8000
H’9000
H’1000
H’2000
H’8000
H’9000
H’0FFE
H’0000
H’2000
H’9000
(b) When reload register updates take effect in the next period (reflected one period later)
Note: This diagram does not show detail timing information.
Count clock
Reload 0 register
Reload 1 register
Counter
Interrupt
by underflow
Timing at which reload 1
and reload 0 registers are updated
Old PWM output period
Operation by old reload value
Reload 0 register
Reload 1 register
F/F output
Write to reload 1
Write to reload 0
(reload 1 data latched)
Enlarged view
Old PWM
output period
Old PWM output period
F/F output
PWM period latched
Reload 1 buffer