
11
11-17
32170/32174 Group User's Manual (Rev. 2.1)
Figure 11.2.3 A-D Converter Related Register Map (3/4)
A-D CONVERTERS
11.2 A-D Converter Related Registers
H’0080 0A84
H’0080 0A86
H’0080 0A88
H’0080 0A8A
H’0080 0A8C
H’0080 0A80
H’0080 0A82
D0
D7
D8
D15
H’0080 0A90
H’0080 0A92
H’0080 0A94
H’0080 0A96
H’0080 0A98
H’0080 0A9A
H’0080 0A9C
H’0080 0A9E
H’0080 0AA0
H’0080 0AA2
H’0080 0AA4
H’0080 0AA6
H’0080 0AA8
H’0080 0AAA
H’0080 0AAC
H’0080 0AAE
A-D1 Single Mode Register 0
(AD1SIM0)
Address
+0 Address
+1 Address
10-bit A-D1 Data Register 0 (AD1DT0)
A-D1 Scan Mode Register 0
(AD1SCM0)
A-D1 Successive Approximation Register (AD1SAR)
A-D1 Comparate Data Register (AD1CMP)
Note: The registers enclosed in thick frames must always be accessed in halfwords.
Blank addresses are reserved.
A-D1 Single Mode Register 1
(AD1SIM1)
A-D1 Scan Mode Register 1
(AD1SCM1)
10-bit A-D1 Data Register 1 (AD1DT1)
10-bit A-D1 Data Register 2 (AD1DT2)
10-bit A-D1 Data Register 3 (AD1DT3)
10-bit A-D1 Data Register 4 (AD1DT4)
10-bit A-D1 Data Register 5 (AD1DT5)
10-bit A-D1 Data Register 6 (AD1DT6)
10-bit A-D1 Data Register 7 (AD1DT7)
10-bit A-D1 Data Register 8 (AD1DT8)
10-bit A-D1 Data Register 9 (AD1DT9)
10-bit A-D1 Data Register 10 (AD1DT10)
10-bit A-D1 Data Register 11 (AD1DT11)
10-bit A-D1 Data Register 12 (AD1DT12)
10-bit A-D1 Data Register 13 (AD1DT13)
10-bit A-D1 Data Register 14 (AD1DT14)
10-bit A-D1 Data Register 15 (AD1DT15)