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| 型號(hào)： | M312L5720DZ3-CB3 |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.7 ns, DMA184 |
| 封裝： | ROHS COMPLIANT, DIMM-184 |
| 文件頁(yè)數(shù)： | 11/28頁(yè) |
| 文件大?。?/td> | 661K |
| 代理商： | M312L5720DZ3-CB3 |
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DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 April 2006
Parameter
Symbol
CC
(DDR400@CL=3.0)
B3
(DDR333@CL=2.5)
A2
(DDR266@CL=2.0)
B0
(DDR266@CL=2.5) Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Row cycle time
tRC
55
60
65
ns
Refresh row cycle time
tRFC
70
72
75
ns
Row active time
tRAS
40
70K
42
70K
45
70K
45
70K
ns
RAS to CAS delay
tRCD
15
18
20
ns
Row precharge time
tRP
15
18
20
ns
Row active to Row active delay
tRRD
10
12
15
ns
Write recovery time
tWR
15
ns
Last data in to Read command
tWTR
2
1
tCK
Clock cycle time
CL=2.0
tCK
-
7.5
12
7.5
12
10
12
ns
CL=2.5
612612
7.5
12
7.5
12
ns
CL=3.0
5
10
-
----
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS-out access time from CK/CK
tDQSCK
-0.55
+0.55
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/CK
tAC
-0.65
+0.65
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput data edge
tDQSQ
-
0.4
-
0.45
-
0.5
-
0.5
ns
22
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.72
1.28
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
ns
13
DQS-in hold time
tWPRE
0.25
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
tCK
DQS-in high level width
tDQSH
0.35
tCK
DQS-in low level width
tDQSL
0.35
tCK
Address and Control Input setup time(fast)
tIS
0.6
0.75
0.9
ns
15, 17~19
Address and Control Input hold time(fast)
tIH
0.6
0.75
0.9
ns
15, 17~19
Address and Control Input setup time(slow)
tIS
0.7
0.8
1.0
ns
16~19
Address and Control Input hold time(slow)
tIH
0.7
0.8
1.0
ns
16~19
Data-out high impedence time from CK/CK
tHZ
-0.65
+0.65
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
11
Data-out low impedence time from CK/CK
tLZ
-0.65
+0.65
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
11
Mode register set cycle time
tMRD
10
12
15
ns
DQ & DM setup time to DQS
tDS
0.4
0.45
0.5
ns
j, k
DQ & DM hold time to DQS
tDH
0.4
0.45
0.5
ns
j, k
Control & Address input pulse width
tIPW
2.2
ns
18
DQ & DM input pulse width
tDIPW
1.75
ns
18
Exit self refresh to non-Read command
tXSNR
75
ns
Exit self refresh to read command
tXSRD
200
tCK
Refresh interval time
tREFI
7.8
us
14
Output DQS valid window
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-ns
21
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
20, 21
Data hold skew factor
tQHS
0.5
0.55
0.75
ns
21
DQS write postamble time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
12
Active to Read with Auto precharge
command
tRAP
15
18
20
Autoprecharge write recovery +
Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
23
12.0 AC Timming Parameters & Specifications
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| M312L6420ETS | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Registered Module |
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