- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296354 > M312L5720BZ0-CB3 256M X 72 DDR DRAM MODULE, 0.7 ns, DMA184 PDF資料下載
參數(shù)資料
| 型號： | M312L5720BZ0-CB3 |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.7 ns, DMA184 |
| 封裝： | ROHS COMPLIANT, DIMM-184 |
| 文件頁數(shù)： | 17/30頁 |
| 文件大小： | 623K |
| 代理商： | M312L5720BZ0-CB3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 June 2005
(V=Valid, X=Don
′t Care, H=Logic High, L=Logic Low)
Note :
1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
A0 ~ A9
A11, A12
Note
Register
Extended MRS
H
X
L
OP CODE
1, 2
Register
Mode Register Set
H
X
L
OP CODE
1, 2
Refresh
Auto Refresh
H
LL
L
H
X
3
Self
Refresh
Entry
L
3
Exit
L
H
LH
HH
X
3
HX
X
3
Bank Active & Row Addr.
H
X
L
H
V
Row Address
(A0~A9, A11,A12)
Read &
Column Address
Auto Precharge Disable
HX
L
H
L
H
V
L
Column
Address
4
Auto Precharge Enable
H
4
Write &
Column Address
Auto Precharge Disable
HX
L
H
L
V
L
Column
Address
4
Auto Precharge Enable
H
4, 6
Burst Stop
H
X
L
H
L
X
7
Precharge
Bank Selection
HX
L
H
L
VL
X
All Banks
X
H
5
Active Power Down
Entry
H
L
HX
X
LV
V
Exit
L
H
X
Precharge Power Down Mode
Entry
H
L
HX
X
LH
HH
Exit
L
H
HX
X
LV
V
DM
H
X
8
No operation (NOP) : Not defined
H
X
HX
X
9
LH
HH
9
16.0 Command Truth Table
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M312L5720DZ3-CB3 | 256M X 72 DDR DRAM MODULE, 0.7 ns, DMA184 |
| M32002AMMJFREQ | VCXO, CLOCK, 150 MHz - 1400 MHz, CMOS OUTPUT |
| M32016BGPJFREQ | VCXO, CLOCK, 150 MHz - 1400 MHz, PECL OUTPUT |
| M32026AUMJFREQ | VCXO, CLOCK, 150 MHz - 1400 MHz, CMOS OUTPUT |
| M32012BGPJFREQ | VCXO, CLOCK, 150 MHz - 1400 MHz, PECL OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M312L5720CZ3-CCC00 | 制造商:Samsung Semiconductor 功能描述:512 DDR SDRAM MODUL X72 BOC(LF) - Trays |
| M312L6420ETS | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Registered Module |
| M312L6420HUS | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Product Guide |
| M312L6420HUS-CB000 | 制造商:Samsung Semiconductor 功能描述:256 DDR SDRAM MODUL X72 TSOP2-400(LF) - Trays |
| M312L6420JUS | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Product Guide |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。