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Under
development
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
35
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Table 1.7.6. Operation of RD, WR, and BHE signals
Status of external data bus
RD
BHE
WR
HL
L
LHL
HLH
LH
H
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Data bus width
A0
H
L
HL
L
LHL
L
HL
H / L
LH
H / L
8-bit
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
16-bit
Not used
Status of external data bus
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
WRH
WRL
RD
Data bus width
16-bit
H
L
H
L
H
L
H
H (Note)
L (Note)
L
Not used
Write 1 byte of data
Read 1 byte of data
Not used
8-bit
(3) Read/write signals
With a 16-bit data bus, bit 2 of the processor mode register 0 (address 000416) select the combinations of
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RD, BHE, and WR signals or RD, WRL, and WRH signals. With a 8-bit full space data bus, use the
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combination of RD, WR, and BHE signals as read/write signals. (Set "0" to bit 2 of the processor mode
register 0 (address 000416).) When using both 8-bit and 16-bit data bus widths and you access an 8-bit
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data bus area, the RD, WR and BHE signals combination is selected regardless of the value of bit 2 of the
processor mode register 0 (address 000416).
Tables 1.7.5 and 1.7.6 show the operation of these signals.
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After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
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When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note).
Note 1: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
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Note 2: When using 16-bit data bus width for DRAM controller, select RD, WRL, and WRH signals.
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Table 1.7.5. Operation of RD, WRL, and WRH signals
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Note: It becomes WR signal.