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Contents for change
Revision
date
Version
Under
development
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
328
Revision history
Page 250 Figure1.28.23 th(BCLK-DB)-->th(CAS-DB)
Page 251 Figure 1.28.24 td(DB-CAS)-->tsu(DB-CAS), th(BCLK-CAS)-->th(BCLK-DB)
Page 252 Figure1.28.25 td(CAS-RAS)-->tsu(CAS-RAS)
Page 255 Table1.29.1 Power supply (under planning)-->delete, Program/erase voltage
f(XIN)-->f(BCLK), 2.7V-5.5V-->delete
144-pin version description addition
Pages 1, 6 Supply voltage --> external ROM version addition
Page 7 (3) Package 144P6Q --> 144P6Q-A
Page 21 Figure 1.4.4 (111) Function select register C 0016 --> 0XXXXXX0
(119) Function select register B3 ?0000??? --> 00000X0X
Similarly, page 202 Figures 1.26.11 When reset ?0000??? --> 00000X0X
Figures 1.26.12 When reset 0016 --> 0XXXXXX0
Page 28 Figure 1.6.2 ROMless version addition
Page 29 Figure 1.6.3 External area 0 to 3 addition
Page 34 Addition
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Page 37 Figure 1.7.4 Input RDY signal at i + 1 cycles for i wait --> RDY signal received timing
for i wait: i +1
Page 46 Figure 1.8.4 System clock control register 0 CM0 --> contents of the Function
changed, Notes 10, 11 addition
Page 48 On the second line from the bottom, 'Although stop mode ... must be set to "1".'
-->addition
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_______ _______
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Page 49 Table 1.8.4 CS0 to CS3 --> CS0 to CS3, BHE
WR, BHE, WRL, WRH, W, CASL
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______
_________
--> WR, WRL, WRH, DW, CASL
Page 52 Table 1.8.6 CM0i: Clock control register 0 (address 000616) bit i, MCDi: Main clock
division register (address 000C16) bit i --> addition
Page 60 Vector table dedicated for emulator
Interrupt vector address (address 00002016 to 00002316)-->... (address
00002016 to 00002216)
Page 69 Interrupt priority
'the interrupt that a request came to most in the first place is accepted at first, and
then,' --> delete
Page 76, 77 From " To rewrite the interrupt control..." to the end of page 77 --> addition
Page 78 "In the stop...released." on the third line from the bottom --> addition
Page 79 Figure 1.10.2 Notes 10, 11 --> addition
Page 94 Figure 1.13.3 Timer Ai register -->Notes 2 to 4 addition, Pulse width modulation
mode (8-bit PWM) --> Values that can be set is changed, Up/down flag --> Note addi-
tion
Page 97 Figure 1.13.6 --> change
Page 98 Table 1.13.3 --> Note 2 addition, Normal processing operation --> Normal pro-
cessing operation (Timer A2 and timer A3), Multiply-by-4 processing operation -->
Multiply-by-4 processing operation (Timer A3 and timer A4)
Page 99 Figure 1.13.7 Timer Ai mode register (When using two-phase pulse signal process-
ing) --> "Note 2 Timer A2 is fixed to ... multiply-by-4 processing operation." is added,
note 3 change
Page 109 Figure 1.14.6 Note 1 It is indeterminate when reset --> addition
Page 112 Figure 1.15.2 Dead time timer-->Note 1 addition, Timer B2 interrupt occurrence
frequency set counter-->Note 3 addition
Rev.E
09/02/'01