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Timers (Timer B)
125
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Under
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Item
Specification
Count source
f1, f2, f8, f32, fC32
Count operation
Down-count
When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1)
n: set value of TBiMR register (i= 0 to 5)
000016 to FFFF16
Count start condition
Set TBiS bit(Note) to “1” (= start counting)
Count stop condition
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing
Timer underflow
TBiIN pin function
I/O port
Read from timer
Count value can be read by reading TBi register
Write to timer
When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Note : The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S
bits are assigned to the TBSR register bit 5 to bit 7.
1. Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 1.15.1). Figure 1.15.4
Table 1.15.1. Specifications in Timer Mode
Timer Bi mode register (i= 0 to 5)
Symbol
Address
After reset
TB0MR to TB2MR
039B16 to 039D16
00XX00002
TB3MR to TB5MR
035B16 to 035D16
00XX00002
Bit name
Function
Bit symbol
RW
b7
b6
b5
b4
b3
b2
b1
b0
Operation mode select bit
0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0
Has no effect in timer mode
Can be set to “0” or “1”
MR2
MR1
MR3
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
TCK1
TCK0
Count source select bit
0
TB0MR, TB3MR registers
Must be set to “0” in timer mode
b7 b6
RW
RO
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
When write in timer mode, set to “0”. When read in timer mode, its
content is indeterminate.
Figure 1.15.4. TBiMR Register in Timer Mode