![](http://datasheet.mmic.net.cn/30000/M30622F8PGP_datasheet_2359050/M30622F8PGP_217.png)
Programmable I/O Ports
217
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Under
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Port Pi register (i=0 to 7 and 9 to 13) (Note 2, 3)
Symbol
Address
After reset
P0 to P3
03E016, 03E116, 03E416, 03E516
Indeterminate
P4 to P7
03E816, 03E916, 03EC16, 03ED16
Indeterminate
P9 to P12
03F116, 03F416, 03F516, 03F816
Indeterminate
P13
03F916
Indeterminate
Bit name
Function
Bit symbol
RW
b7
b6
b5
b4
b3
b2
b1
b0
Pi_0
Port Pi0 bit
Pi_1
Port Pi1 bit
Pi_2
Port Pi2 bit
Pi_3
Port Pi3 bit
Pi_4
Port Pi4 bit
Pi_5
Port Pi5 bit
Pi_6
Port Pi6 bit
Pi_7
Port Pi7 bit
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
0 : “L” level
1 : “H” level (Note 1)
(i = 0 to 7 and 9 to 13)
Port P8 register
Symbol
Address
After reset
P8
03F016
Indeterminate
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
P8_0
Port P80 bit
P8_1
Port P81 bit
P8_2
Port P82 bit
P8_3
Port P83 bit
P8_4
Port P84 bit
P8_5
Port P85 bit
P8_6
Port P86 bit
P8_7
Port P87 bit
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register (except for P85)
0 : “L” level
1 : “H” level
Note 1: Since P70 and P71 are N-channel open drain ports, the data is high-impedance.
RW
RO
Note 2: During memory extension and microprocessor modes, the Pi register for the pins
functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE,
ALE, RDY, HOLD, HLDA and BCLK) cannot be modified.
Note 3: To use ports P11 to P14, set the PUR3 register’s PU37 bit to “1” (enable). If this bit is set to
“0” (disable), the P11 to P14 registers are cleared to ‘0016’ and the P11 to P14 pins are
placed in the high-impedance state.
Figure 1.25.8. P0 to P13 Registers