參數(shù)資料
型號: M27C405-100B1TR
廠商: 意法半導體
英文描述: 4 Mbit 512Kb x 8 OTP EPROM
中文描述: 4兆位× 8檢察官辦公室512KB的存儲器
文件頁數(shù): 2/15頁
文件大?。?/td> 99K
代理商: M27C405-100B1TR
A1
A0
Q0
Q1
Q2
VSS
A7
A6
A5
A4
A3
A2
A13
A8
A9
A11
G
A10
E
Q7
Q6
A14
Q5
Q4
Q3
A17
VPP
A16
A15
A12
A18
VCC
AI01602
M27C405
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Figure 2A. DIPPin Connections
AI01603
A
A8
A9
A11
G
A10
E
Q
17
A1
A0
Q0
Q
Q
Q
Q
A7
A6
A5
A4
A3
A2
9
V
1
A
A13
A
Q7
32
A
V
M27C405
A
A14
Q
25
V
Figure 2B. LCC PinConnections
A1
A2
A0
Q0
A7
A6
A5
A4
A3
A13
A14
A17
VPP
VCC
A10
E
A8
A9
Q7
Q6
A11
G
Q5
Q4
Q1
Q2
Q3
VSS
A18
A16
A15
A12
AI01604
M27C405
(Normal)
8
9
1
16
17
24
25
32
Figure 2C. TSOPPin Connections
DEVICEOPERATION
Themodesof operationsof theM27C405arelisted
in the OperatingModes table. Asingle power sup-
plyis requiredin the read mode.All inputsare TTL
levels except for V
pp
and 12V on A9 for Electronic
Signature.
Read Mode
The M27C405 has two control functions, both of
which must be logically active in order to obtain
data at the outputs.Chip Enable (E) is the power
control and should be used for device selection.
OutputEnable(G) is the outputcontroland should
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
addresses are stable, the address access time
(t
AVQV
)isequalto thedelayfromEtooutput(t
ELQV
).
Datais availableat theoutputaftera delayof t
GLQV
from the falling edge of G, assuming that E has
been low and the addresseshave been stable for
at least t
AVQV
-t
GLQV
.
Standby Mode
TheM27C405hasa standbymodewhichreduces
the active current from 30mA to 100
μ
A. The
M27C405is placedin the standbymodeby apply-
inga CMOShigh signaltothe Einput.When in the
standbymode,theoutputsareinahighimpedance
state,independentof the G input.
2/15
M27C405
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