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參數(shù)資料
| 型號(hào)： | M25PE40VMW6G |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 512K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.208 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 5/62頁 |
| 文件大?。?/td> | 565K |
| 代理商： | M25PE40VMW6G |
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M25PE40
Operating features
13/62
4.3
A fast way to modify data
The Page Program (PP) instruction provides a fast way of modifying data (up to 256
contiguous bytes at a time), provided that it only involves resetting bits to 0 that had
previously been set to ‘1’.
This might be:
●
when the designer is programming the device for the first time
●
when the designer knows that the page has already been erased by an earlier Page
Erase (PE) or Sector Erase (SE) instruction. This is useful, for example, when storing a
fast stream of data, having first performed the erase cycle when time was available
●
when the designer knows that the only changes involve resetting bits to ‘0’ that are still
set to ‘1’. When this method is possible, it has the additional advantage of minimizing
the number of unnecessary erase operations, and the extra stress incurred by each
page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Section 6.10: Page
4.4
Polling during a Write, Program or Erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for
the worst case delay (tPW, tPP, tPE, or tSE). The Write In Progress (WIP) bit is provided in the
Status Register so that the application program can monitor its value, polling it to establish
when the previous cycle is complete.
4.5
Reset
An internal Power-on Reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (Reset) Low during the power-on process, and only
driving it High when VCC has reached the correct voltage level, VCC(min).
4.6
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write). The device then goes
in to the Standby Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to ICC2. The
device remains in this mode until the Release from Deep Power-down instruction is
executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M25PE40-VMW6G | 功能描述:閃存 4 Mbit Lo Vltg Page Erasable Seral 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M25PE40-VMW6G_NUD | 制造商:Micron Technology Inc 功能描述: |
| M25PE40VMW6P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout |
| M25PE40-VMW6P | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:4 Mbit, page-erasable serial Flash memory with byte alterability, 75 MHz SPI bus, standard pinout |
| M25PE40VMW6TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout |
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