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參數(shù)資料
| 型號： | M12L16161A-5T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 512K x 16Bit x 2Banks Synchronous DRAM |
| 中文描述： | 為512k × 16Bit的X 2Banks同步DRAM |
| 文件頁數(shù)： | 21/27頁 |
| 文件大?。?/td> | 566K |
| 代理商： | M12L16161A-5T |
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M12L16161A
Elite Semiconductor Memory Technology Inc.
P.
21
Publication Date : J an. 2000
Revision : 1.3u
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page
*Note:
1.Burst can’t end in full page mode, so auto precharge can’t issue.
2.About the valid DQs after burst stop, it is same as the case of RASinterrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RASinterrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
3.Burst stop is valid at every burst length.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
C L O C K
C K E
A D D R
D Q
D Q M
A1 0 / A P
B A
R A a
C A a
C Ab
R A a
Q A a 0 Q A a 1
Q A b 1
Q A b 0
QA b2
*N ot e1
R ow A c t ive
(A - B a n k )
R ea d
(A - B a n k )
B u r s t S t op R ea d
(A - B a n k )
: D on 't C a r e
H IG H
C L =2
C L =3
Q A a 2 Q A a 3 Q A a 4
QA b 3 QA b4 Q A b 5
Q A a 0 Q A a 1
Q A b 1
Q A b 0
QA b 2
Q A a 2 Q A a 3 Q A a 4
Q A b3 Q A b 4 Q A b 5
1
1
2
2
Pr ec h a r g e
(A - B a n k )
CS
RAS
CAS
WE
*Note2
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M12L16161A-5TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-5TG2Q | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks |
| M12L16161A-5TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-6T | 制造商:ESI 功能描述: |
| M12L16161A-7BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
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