- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376119 > M12L16161A-5.5T (Electronic Theatre Controls, Inc.) 512K x 16Bit x 2Banks Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | M12L16161A-5.5T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 512K x 16Bit x 2Banks Synchronous DRAM |
| 中文描述： | 為512k × 16Bit的X 2Banks同步DRAM |
| 文件頁數(shù)： | 5/27頁 |
| 文件大?。?/td> | 566K |
| 代理商： | M12L16161A-5.5T |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
M12L16161A
Elite Semiconductor Memory Technology Inc.
P.
5
Publication Date : J an. 2000
Revision : 1.3u
AC OPERATING TEST CONDITIONS
(V
DD
=3.3V
±
0.3V,T
A
= 0 to 70 C
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
)
Value
2.4 / 0.4
1.4
tr / tf = 1 / 1
1.4
See Fig.2
Unit
V
V
ns
V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
-5.5
11
16
Parameter
Symbol
-4.3
8.6
12.9
-5
10
15
-6
12
16
-7
14
16
-8
16
20
Unit
Note
Row active to row active delay
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
ns
ns
1
1
RAS to CASdelay
Row precharge time
12.9
15
16
18
20
20
ns
1
34.4
40
40
42
42
48
ns
us
ns
1
Row active time
100
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Number of valid output data
47.3
55
60
60
63
68
1
2
2
2
3
1
1
1
1
1
1
CLK
CLK
CLK
CLK
CAS latency=3
CAS latency=2
ea
4
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
4.
Minimum delay is required to complete write.
4.
All parts allow every cycle column address change.
4.
In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
3.3V
Output
(Fig.2) AC Output Load Circuit
30 pF
Vtt =1.4V
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
30 pF
Output
(Fig.1) DC Output Load circuit
Z0=50
è
870
è
1200
è
50
è
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M12L16161A-5T | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-6T | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-7T | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-8T | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12L64322A | 512K x 32 Bit x 4 Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12L16161A-5T | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-5TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-5TG2Q | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks |
| M12L16161A-5TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-6T | 制造商:ESI 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。