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參數(shù)資料
| 型號(hào)： | LXP710PE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 53/84頁 |
| 文件大?。?/td> | 1108K |
| 代理商： | LXP710PE |
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HDSL Framer/Mapper for 1168 kbps Applications
—
LXP710
Datasheet
53
Loop 2 QRSS Test Pattern Error Counter (2 bytes)
Address: 5A
Abbreviation: L2PATECH
Read
Address: 5B
Abbreviation: L2PATECL
Read
Loop 2 Mux Restart Counter Register
Address: 5C
Abbreviation: MX2RSCNTR
Read
Table 83. Demux Loop 2 BPV Error Count
Bit
Name
Default
Description
<7:0>
BPV2EC<7:0>
0
Demux Loop 2 BPV Error Counter. This 8-bit counter increments each time
one or more errors are detected on the demux Loop 2 BPV bits. After a
microprocessor read, the counter is cleared. This counter is disabled when the
LOSW2 signal is High, and automatically stops at 0FFh to prevent overflow.
Table 84. Loop 2 QRSS Test Pattern Error Counter (High byte)
Bit
Name
Default
Description
<7:0>
PAT2EC<15:8>
0
Loop 2 Test Pattern Error Counter (High byte). This 16-bit counter increments
each time the demux test pattern receiver detects a pattern error. When the
upper byte is read, the current count of both bytes is latched and the counter
is cleared. This counter is disabled when pattern sync is lost. This counter
does not stop counting at 0FFFFh, however, a latched overflow status bit is
provided in the General Interrupt Vector Status register.
Table 85. Loop 2 QRSS Test Pattern Error Counter (Low byte)
Bit
Name
Default
Description
<7:0>
PAT2EC<7:0>
0
Loop 2 Test Pattern Error Counter (Low byte). The lower byte is latched when
the upper byte is read. Therefore, this byte must be read last when reading the
16-bit Pattern Error Counter.
Table 86. Loop 2 Mux Restart Counter
Bit
Name
Default
Description
<7:0>
n/a
0
Loop 2 mux restart counter. Increments each time the mux loop has been
restarted.
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