- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45001 > LUCW3000CCN-TR PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO14 PDF資料下載
參數(shù)資料
| 型號： | LUCW3000CCN-TR |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO14 |
| 封裝： | TSSOP-14 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大小： | 326K |
| 代理商： | LUCW3000CCN-TR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
Advance Data Sheet
December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Lucent Technologies Inc.
17
PLL Lock-Detect Function
The W3000 provides a basic lock-detect function for fault finding or for system specification requirements.
Inside the W3000, the length of the up or down pulses applied to the loop filter is compared with a reference
clock period. If the current pulses are shorter than a reference clock period for 15 consecutive comparison
periods, the LD line is asserted. If a current pulse is detected that is longer than a reference clock period, the LD
line is unset.
The LD line gives a signal to indicate a PLL fault condition. It does not provide a true loop-locked output. For
example, in a GSM system with a reference clock of 13 MHz and a comparison frequency of 200 kHz, the
current pulses only have to be less than 1/65 of a cycle for 15 consecutive times for the LD line to be asserted.
This equates to ~0.4 of phase. In the worst case, if the phase stays inside this limit, moving from one extreme to
the other, the frequency will only be within 0.2%, i.e., 4 MHz on a 2 GHz VCO.
The LD output from the W3000 is a standard logic signal and requires no external comparison or R-C filters.
Typical Performance Characteristics
UHF
SOURCE
0.047 F
100 pF
+VDDC
100 pF
+VDD
C
REFERENCE
SOURCE
0.01 F
10 MHz REF
442
CURRENT
METER
VDDC/2
50
6.8 pF
50
LAT
DAT
CLK
PWRDN
REF_IN
LOCK DET
RES
VDDC
CPOUT
VSS1
VSS2
MAIN_IN
VDD2
VDD1
RREF = 18 k
VDDC
Figure 8. MAIN_IN and REF_IN Sensitivity Test Circuit Diagram
MAIN_IN and REF_IN are set to cause a small beat frequency at the phase detector input. This generates a
sawtooth signal at the charge pump output of known slope. The amplitude of the UHF source is decreased. The
sensitivity limit is reached when the slope of this waveform deviates from the calculated value. This is then
repeated for the reference source.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LUW025F-S | 1-OUTPUT 16.5 W DC-DC REG PWR SUPPLY MODULE |
| LUW025F6 | 1-OUTPUT 16.5 W DC-DC REG PWR SUPPLY MODULE |
| LUW025F | 1-OUTPUT 16.5 W DC-DC REG PWR SUPPLY MODULE |
| LUW025A-S | 1-OUTPUT 25 W DC-DC REG PWR SUPPLY MODULE |
| LUW025F8 | 1-OUTPUT 16.5 W DC-DC REG PWR SUPPLY MODULE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LUCW3011FCL | 制造商:AGERE 制造商全稱:AGERE 功能描述:1 GHz Quadrature Modulator |
| LUCW3020CCS | 制造商:AGERE 制造商全稱:AGERE 功能描述:GSM Multiband RF Transceiver |
| LUCW3020CCS-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:GSM Multiband RF Transceiver |
| LUCW3030ACA | 制造商:AGERE 制造商全稱:AGERE 功能描述:W3030 3 V Dual-Mode IF Cellular Receiver |
| LUCW3030ACA-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:W3030 3 V Dual-Mode IF Cellular Receiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。