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| 型號： | LUCW3000CCN-TR |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO14 |
| 封裝： | TSSOP-14 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大小： | 326K |
| 代理商： | LUCW3000CCN-TR |
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Advance Data Sheet
W3000 PLL Dual-Band Frequency Synthesizer
December 1999
Lucent Technologies Inc.
16
MAIN Register (continued)
Table 21. M1:M11: Programmable Main Counter Divide Ratio (Bits 9 to 19)
M11
Bit 19
M10
Bit 18
M9
Bit 17
M8
Bit 16
M7
Bit 15
M6
Bit 14
M5
Bit 13
M4
Bit 12
M3
Bit 11
M2
Bit 10
M1
Bit 9
Divide
Ratio
M
0
1
0
2
0
1
3
.
0
1
255
.
1
2047
The main counter divides the frequency of the prescaler output signal and sources the divided signal to the
phase comparator.
Table 22. EN2: Synthesizer Enable (Bit 22)
PWRDN
EN2
Mode
H
0
Powerdown
H
1
Enable
L
0
Powerdown
L
1
Powerdown
The REF register also contains an enable bit, EN1 (see Table 16). The W3000 is enabled or powered down with
either the REF or MAIN register, whichever was programmed more recently. The contents of the MAIN and REF
registers are maintained in powerdown mode, providing supply voltages are maintained.
Table 23. B: Band Select (Bit 23)
B
Band
0
Band 1
1
Band 2
In dual-band operation, this bit allows the use of one loop filter by setting the charge pump current to correspond
to the frequency of the band selected. See Table 12 for the available charge pump current settings.
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