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參數(shù)資料
| 型號： | LTVA |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10 |
| 中文描述： | 1-/2-Channel 20位ADC的無延遲UPower采用MSOP - 10 |
| 文件頁數(shù)： | 30/32頁 |
| 文件大小： | 375K |
| 代理商： | LTVA |
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30
LTC2421/LTC2422
24212f
APPLICATIOU
Below 4.2V, the LTC1535’s driver outputs Y and Z are in a
high impedance state, allowing the 1k
pull-down to de-
fine the logic state at SCK. When the LTC2422 first be-
comes active, it samples SCK; a logic “0” provided by the
1k
pull-down invokes the external serial clock mode. In
this mode, the LTC2422 is controlled by a single clock line
from the nonisolated side of the barrier, through the
LTC1535’s driver output Y. The entire power-up sequence,
W
U
U
+
+
F
O
SCK
SDO
CS
GND
V
CC
FS
SET
CH1
CH0
ZS
SET
LTC2422
24212 F36
LT1761-5
GND
10
μ
F
10V
TANT
10
μ
F
10V
TANT
+
10
μ
F
16V
TANT
+
10
μ
F
10V
TANT
10
μ
F
1
μ
F
T1
1/2 BAT54C
1/2 BAT54C
ISOLATION
BARRIER
= LOGIC COMMON
= FLOATING COMMON
T1 = COILTRONICS CTX02-14659
OR SIEMENS B78304-A1477-A3
1k
2
2
1
2
1
1
1
2
2
2
2
10
μ
F
CERAMIC
A
B
Y
Z
RO
RE
DE
DI
V
CC2
ST2
G1
V
CC1
G2
ST1
“SDO”
“SCK”
LOGIC 5V
IN
OUT
SHDN
BYP
LTC1535
Figure 36. Complete, Isolated 20-Bit Data Acquisition System
from the time power is applied to V
CC1
until the LT1761’s
output has reached 5V, is approximately 1ms.
Data returns to the nonisolated side through the LTC1535’s
receiver at RO. An internal divider on receiver input B sets
a logic threshold of approximately 3.4V at input A, facili-
tating communications with the LTC2422’s SDO output
without the need for any external components.
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