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參數(shù)資料
| 型號(hào)： | LTVA |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10 |
| 中文描述： | 1-/2-Channel 20位ADC的無延遲UPower采用MSOP - 10 |
| 文件頁(yè)數(shù)： | 21/32頁(yè) |
| 文件大?。?/td> | 375K |
| 代理商： | LTVA |
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21
LTC2421/LTC2422
24212f
APPLICATIOU
W
U
U
Figure 12. Internal Serial Clock, Autostart Operation
V
CC
F
O
FS
SET
ZS
SET
SCK
CH1
SDO
GND
CS
REFERENCE VOLTAGE
ZS
SET
+ 0.1V TO V
CC
ANALOG INPUT RANGE
ZS
SET
– 0.12V
TO
SET
+ 0.12V
REF
(V
REF
= FS
SET
– ZS
SET
)
0V TO FS
SET
– 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1
μ
F
1
10
9
8
7
6
C
EXT
2
3
4
5
2.7V TO 5.5V
LTC2422
V
CC
V
CC
10k
SDO
Hi-Z
Hi-Z
SCK
(INTERNAL)
CS
V
CC
GND
2420 F12
BIT 0
SIG
BIT 21
BIT 22
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
EOC
BIT 23
Figure 13. CS Capacitance vs t
SAMPLE
Figure 14. CS Capacitance
vs Output Rate
CAPACITANCE ON CS (pF)
1
5
6
7
1000
10000
24212 F13
4
3
10
100
100000
2
1
0
t
S
V
CC
= 5V
V
CC
= 3V
CAPACITANCE ON CS (pF)
1
0
S
μ
A
R
)
50
100
150
200
250
300
10
100
1000
10000
24212 F15
100000
V
CC
= 5V
V
CC
= 3V
to take advantage of exceptional accuracy and low supply
current.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
In order to preserve the LTC2421/LTC2422’s accuracy, it
is very important to minimize the ground path impedance
which may appear in series with the input and/or reference
signal and to reduce the current which may flow through
this path. The GND pin should be connected to a low
CAPACITANCE ON CS (pF)
1
0
S
μ
A
R
)
50
100
150
200
250
300
10
100
1000
10000
24212 F15
100000
V
CC
= 5V
V
CC
= 3V
Figure 15. CS Capacitance
vs Supply Current
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