- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45001 > LTM9005IV-AB#PBF (LINEAR TECHNOLOGY CORP) SPECIALTY ANALOG CIRCUIT, PBGA204 PDF資料下載
參數(shù)資料
| 型號： | LTM9005IV-AB#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA204 |
| 封裝： | 22 X 15 MM, 4.32 MM HEIGHT, LEAD FREE, MO-222, LGA-204 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 468K |
| 代理商： | LTM9005IV-AB#PBF |
LTM9005
17
9005p
applicaTions inForMaTion
to phase noise. The LVDS or PECL to CMOS translators
providelittledegradationbelow70MHz,butat140MHzwill
degrade the SNR compared to the transformer solution.
The nature of the received signals also has a large bearing
on how much SNR degradation will be experienced. For
high crest factor signals such as WCDMA or OFDM, the
use of these translators will have a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed
to ground through a capacitor close to the ADC if the
differential signals originate on a different plane. The
use of a capacitor at the input may result in peaking, and
depending on transmission line length may require a 10Ω
to 20Ω series resistor to act as both a lowpass filter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for reflections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the ADC is 125Msps.
The lower limit of the sample rate is determined by the
droop of the sample-and-hold circuits. The pipelined ar-
chitecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
thecapacitors.Thespecifiedminimumoperatingfrequency
for the LTM9005 is 1Msps.
Clock Duty Cycle Stabilizer
An optional clock duty cycle stabilizer circuit ensures high
performance even if the input clock has a non 50% duty
cycle.Usingtheclockdutycyclestabilizerisrecommended
formostapplications.Tousetheclockdutycyclestabilizer,
the MODE pin should be connected to 1/3VDD or 2/3VDD
using external resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and
the internal falling edge is generated by a phase-locked
loop. The input clock duty cycle can vary from 40% to
60% and the clock duty cycle stabilizer will maintain a
constant 50% internal duty cycle. If the clock is turned off
for a long period of time, the duty cycle stabilizer circuit
will require a hundred clock cycles for the PLL to lock
onto the input clock.
Forapplicationswherethesamplerateneedstobechanged
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50% (±5%) duty cycle.
GAIN Control Input
The total receiver gain is continuously adjustable using a
PIN diode. Maximum gain is set by forcing GAIN to VCC1.
Figure 9. CLK Driver Using an LVDS or PECL to CMOS Converter
Figure 10. LVDS or PECL CLK Drive Using a Transformer
CLK
100
0.1F
4.7F
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
9005 F09
LTM9005
CLK
5pF-30pF
ETC1-1T
0.1F
VCM
FERRITE
BEAD
DIFFERENTIAL
CLOCK
INPUT
9005 F10
LTM9005
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LUCW3000ACN-TR | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO14 |
| LUCW3000ACN | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO14 |
| LUCW3000ACN | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO14 |
| LUCW3000CCN | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO14 |
| LUCW3000CCN-TR | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTM9006-14 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 65Msps/40Msps/25Msps Low Power Octal ADCs |
| LTM9006CY-14#PBF | 制造商:Linear Technology 功能描述:IC ADC 14BIT SPI/SRL 25M 140-BGA 制造商:Linear Technology 功能描述:ADC 8CH 1.8V 14BIT 25MSPS 制造商:Linear Technology 功能描述:ADC, 14BIT, 25MSPS, SPI, BGA-140; Resolution (Bits):14bit; Sampling Rate:25MSPS; Supply Voltage Type:Single; Supply Voltage Min:1.7V; Supply Voltage Max:1.9V; Supply Current:175mA; Digital IC Case Style:BGA; No. of Pins:140 ;RoHS Compliant: Yes |
| LTM9006IY-14#PBF | 制造商:Linear Technology 功能描述:IC ADC 14BIT SPI/SRL 25M 140-BGA 制造商:Linear Technology 功能描述:MS-uModule, 14-bit, 25Msps, 1.8V Octal ADC, Serial LVDS Outputs |
| LTM9007-14 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 65Msps/40Msps/25Msps Low Power Octal ADCs |
| LTM9007CY-14#PBF | 制造商:Linear Technology 功能描述:IC ADC 14BIT SPI/SRL 40M 140-BGA 制造商:Linear Technology 功能描述:ADC 8CH 1.8V 14BIT 40MSPS 制造商:Linear Technology 功能描述:ADC, 14BIT, 40MSPS, SPI, BGA-140; Resolution (Bits):14bit; Sampling Rate:40MSPS; Supply Voltage Type:Single; Supply Voltage Min:1.7V; Supply Voltage Max:1.9V; Supply Current:232mA; Digital IC Case Style:BGA; No. of Pins:140 ;RoHS Compliant: Yes |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。