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參數(shù)資料
| 型號： | LTM9005IV-AB#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA204 |
| 封裝： | 22 X 15 MM, 4.32 MM HEIGHT, LEAD FREE, MO-222, LGA-204 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大小： | 468K |
| 代理商： | LTM9005IV-AB#PBF |
LTM9005
19
9005p
applicaTions inForMaTion
Table 4. MODE Pin Function
MODE PIN
OUTPUT FORMAT
CLOCK DUTY CYCLE
STABILIZER
0
Straight Binary
Off
1/3VDD
Straight Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overflow Bit
When OF outputs a logic high the converter is either over-
ranged or underranged.
Output Clock
The ADC has a delayed version of the CLK input available
asadigitaloutput,CLKOUT.ThefallingedgeoftheCLKOUT
pin can be used to latch the digital output data.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same supply that powers the logic being driven.
For example, if the converter drives a DSP powered by a
1.8V supply, then OVDD should be tied to that same 1.8V
supply.
OVDD can be powered with any voltage from 500mV up
to the VDD of the part. OGND can be powered with any
voltage from GND up to 1V and must be less than OVDD.
The logic outputs will swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to allow
the outputs to be enabled and disabled during full speed
operation. The output Hi-Z state is intended for use during
long periods of inactivity.
Shutdown Modes
The LTM9005 provides several levels of shutdown. The
mixer, both amplifiers and the ADC can all be shut down
independently. Furthermore, the ADC may be placed in
shutdown or nap modes to conserve power. Connecting
ADCSHDNtoGNDresultsinnormaloperation.Connecting
ADCSHDN to VDD and OE to VDD results in sleep mode,
which powers down all circuitry including the reference
and the ADC typically dissipates 1mW. When exiting
sleep mode, it will take milliseconds for the output data
to become valid because the reference capacitors have to
recharge and stabilize. Connecting ADCSHDN to VDD and
OE to GND results in nap mode and the ADC typically dis-
sipates 30mW. In nap mode, the on-chip reference circuit
is kept on, so that recovery from nap mode is faster than
that from sleep mode, typically taking 100 clock cycles. In
both sleep and nap modes, all digital outputs are disabled
and enter the Hi-Z state.
Amplifier Shutdown
When the ADC is in sleep or nap mode, it is recommended
to shut down both the first and second amplifiers using
their respective shutdown pins, AMP1SHDN and AMP-
2SHDN. Connecting AMPSHDN to GND results in normal
operation. Connecting AMP1SHDN to VCC2 disables the
amplifier preceding the SAW filter and connecting AMP-
2SHDN to VCC3 disables the amplifier following the SAW
filter. It is recommended to tie AMP1SHDN, AMP2SHDN
and ADCSHDN together and control with 3V logic.
Mixer Enable Interface
The mixer is enabled and shut down differently than the
other functions in the LTM9005. The voltage necessary to
turn on the mixer is 2.7V. To disable the mixer, the enable
voltage must be less than 0.3V. If the EN pin is allowed
to float, the mixer will tend to remain in its last operating
state. Thus it is not recommended that the enable function
be used in this manner. If the shutdown function is not
required, then the EN pin should be connected directly
to VCC1.
Supply Sequencing
The VCC pins provide the supplies to the mixer and both
amplifiers. The VDD pin provides the supply to the ADC.
Each VCC pin is brought out separately and internally
bypassed. The mixer, both amplifiers and the ADC are
separate integrated circuits within the LTM9005; however,
there are no supply sequencing considerations beyond
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