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參數(shù)資料
| 型號： | LTC4216IDE#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 17/26頁 |
| 文件大?。?/td> | 311K |
| 描述： | IC CNTRLR HOT SWAP 12-DFN |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 2.3 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 12-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 12-DFN（4x3） |
| 包裝： | 帶卷 (TR) |
LTC4216
17
4216fa
For more information www.linear.com/LTC4216
applicaTions inForMaTion
Power-Up into an Output-Short
Figure 10 shows the timing diagram in the case when the
output is a dead short during power-up. As GATE ramps
up at time point 6, the MOSFET current increases due to
the output short causing the voltage drop across the sense
resistor to rise above 25mV. FILTER sources 60礎, charg-
ing the external capacitor. At time point 7, GATE regulates
to limit the output current to 40mV/R
SENSE
. If the output
continues to be in analog current limit when the FILTER
pin voltage reaches its threshold (1.253V) at time point
8, the circuit breaker trips and GATE is pulled low. The
device latches-off and FAULT is pulled low, indicating a
fault condition. The FILTER capacitor discharges through
a 2.4礎 pull-down until the device resets.
Resetting the Electronic Circuit Breaker
When the LTC4216s electronic circuit breaker is tripped
during a fault condition, FAULT is asserted low and the
RESET, SS and GATE pins are all pulled to ground. This is
shown in the timing diagram of Figure 11. The LTC4216
remains latched-off until the external fault is cleared. To
clear the internal fault latch and restart the device, pull
the ON pin low (< 0.4V) at time point 4 for at least 100祍,
after which the FAULT will go high at time point 5. Tog-
gling the ON pin from low to high (> 0.8V) initiates a new
start-up cycle.
Sense Resistor Considerations
The circuit breaker trip threshold of 25mV and the value
of the sense resistor, R
SENSE
, connected between the
SENSEP and SENSEN pins, determine the trip current level
as given by Equation (10). If the fault current level exceeds
the analog current limit, the current is limited to a value
given by Equation (11). Should the overload condition exist
for more than one fault filter delay as given by Equation
(2), the circuit breaker trips and the device is latched-off.
I
V
R
mV
R
TRIP CB
CB TH
( )
( )
=
=
25
(10)
I
V
R
mV
R
ACL
ACL TH
=
=
( )
40
(11)
For a new circuit design, the sense resistor value is first
calculated from the maximum operating load current under
normal conditions and the minimum circuit breaker trip
threshold. This is given by:
R
V
I
mV
I
SENSE
CB THMIN
LOAD MAX
LOAD MAX
=
=
( , )
( )
.
21 5
(12)
Figure 10. Power-Up into an Output-Short and
Circuit Breaker Trips
Figure 11. Mild Overcurrent Circuit Breaker Trips Followed by
Device Reset
TIMER
2.4礎
2礎
40mV
25mV
10礎
10礎
1礎
1
2 3 4 5 6 7
8
4216 F10
0.8V
TRACKS SS RAMP
FPD
60礎
SENSEP-SENSEN
FILTER
SS
GATE
V
OUT
ON
FAULT
RESET
V
FILT(TH)
V
TMR(TH)
V
GATE
V
OUT
< V
GS(TH)
FAULT
FILTER
DELAY
GATE
REGULATING
2.4礎
<40mV
25mV
4216 F11
FPD
60礎
t
RST(ONLO)
V
FILT(TH)
SENSEP-SENSEN
FILTER
FAULT
RESET
SS
GATE
V
OUT
1
ON
0.4V
POWER BAD
V
FB
< 0.6V
2 3
4
5
MILD
OVERCURRENT
FAULT LATCH
RESET
CIRCUIT BREAKER TRIPS
AND LATCHED-OFF
RESET PULLED LOW
DUE TO POWER BAD
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