參數(shù)資料
型號： LTC4216IDE#TRPBF
廠商： Linear Technology
文件頁數(shù)： 14/26頁
文件大小： 311K
描述： IC CNTRLR HOT SWAP 12-DFN
標(biāo)準(zhǔn)包裝： 2,500
類型： 熱交換控制器
應(yīng)用： 通用
內(nèi)部開關(guān)： 無
電源電壓： 2.3 V ~ 6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 12-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 12-DFN（4x3）
包裝： 帶卷 (TR)
LTC4216
14
4216fa
For more information www.linear.com/LTC4216
applicaTions inForMaTion
Normal Power-Up and Power-Down
Figure 8 illustrates the timing diagram for a normal power-
up sequence in the case where a printed circuit board is
inserted into a live backplane.
At time point 1, the bias supply (V
CC
) ramps up and en-
ables the device when the supply voltage rises above the
undervoltage lockout threshold (2.12V). At time point 2,
SENSEP supply, together with the ON pin, ramp up and
start the first timing cycle when the ON pin voltage ex-
ceeds 0.8V. The TIMER capacitor is allowed to ramp up
with 2礎(chǔ) pull-up once all these conditions are met: GATE
< 0.2V, FILTER < 0.2V, TIMER < 0.2V, SS < 0.2V. At time
point 3, TIMER reaches the V
TMR(TH)
 threshold and the
first timing cycle terminates. The electronic circuit breaker
is enabled and TIMER capacitor is quickly discharged. At
time point 4 checks are made for TIMER, GATE, FILTER and
SS < 0.2V, 擵
SENSE
 below 25mV and FAULT high before
a GATE ramp-up cycle begins. GATE is held low by the
analog current limit amplifier as SS capacitor ramps up
with a 10礎(chǔ) current source. SS switches to 1礎(chǔ) pull-up
for a slower ramp rate when it crosses the input offset
voltage of the ACL amplifier. At this time point, the ACL
amplifier releases the GATE and allows it to ramp up with
a 20礎(chǔ) pull-up. At time point 6, when the GATE voltage
reaches the turn-on threshold of the external MOSFET,
current begins flowing into the load capacitor. The MOSFET
current level at this time point is controlled by the ACL
amplifier and the GATE ramp is slowed down. SS switches
the pull-up current from 1礎(chǔ) to 10礎(chǔ) for a normal ramp
rate. Between time points 6 and 7, the ACL amplifier servos
the GATE voltage to track the SS ramp rate, limiting the
slew rate of the load current. At time point 7, SS reaches
its final value and GATE continue to ramp up with the 20礎(chǔ)
pull-up if the load current is not in analog current limit.
At time point 8, the FB pin voltage exceeds 0.6V and the
second timing cycle is started. When the conditions of
TIMER < 0.2V, 擵
SENSE
 < 25mV and FAULT high are met,
the TIMER capacitor is allowed to ramp up. When TIMER
reaches the V
TMR(TH)
 threshold at time point 9, RESET
goes high, indicating to the system controller that power
is good. After this, the TIMER is held low.
When the ON pin voltage falls below (V
ON(TH)
  擵
ON(HYST)
)
threshold (0.72V), it initiates a power-down sequence. At
time point 11, GATE is discharged by both the ACL ampli-
fier and a 100礎(chǔ) current source pull-down, causing the
output voltage to fall gradually. When the FB pin voltage
falls below 0.6V at time point 12, RESET goes low after a
glitch filter delay (see the section on FB glitch filtering),
indicating that power is bad. When the ON pin voltage falls
below 0.4V, the device resets and GATE is pulled low by
a strong pull-down device.
Soft-Start with Analog Current Limiting
When a very large output load capacitor is connected
during soft-start, the GATE voltage is servoed to regulate
the inrush current to 擵
ACL(TH)
/R
SENSE
. This is illustrated
in the timing diagram of Figure 9. After the initial timing
cycle, the GATE is allowed to ramp up, tracking the SS
ramp rate between time points 5 and 8. At time point 7,
when the load current builds up as the GATE pin voltage
increases, the voltage across the sense resistor rises above
擵
CB(TH)
 (25mV typical). The FILTER capacitor starts to
charge up by a 60礎(chǔ) current source pull-up. At time point
8, SS reaches its final value at the end of SS ramp cycle.
This allows the GATE to be regulated by the ACL amplifier
at 擵
ACL(TH)
 (40mV typical) across the sense resistor,
R
SENSE
, limiting the inrush to:
 
I
mV
R
LIMIT
EN E
=
40
 
(9)
The FILTER pin voltage continues to rise as the load ca-
pacitor charges up with the limited load current. At time
point 9, the FB pin voltage exceeds 0.6V, but the second
timing cycle is not allowed to start as the voltage across
the sense resistor exceeds 25mV. At time point 10, the load
current falls as the load capacitor is near full charge and
the voltage across the sense resistor drops below 40mV.
The analog current limit loop shuts off and the GATE ramps
further till its final value. The FILTER capacitor discharges
by a 2.4礎(chǔ) pull-down when the voltage across the sense
resistor falls below 25mV at time point 11. The duration
between time points 7 and 11 must be shorter than one
circuit breaker delay, as given by Equation (2), to avoid
a fault time-out during GATE ramp-up for very large load
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