參數(shù)資料
型號： LTC4216IDE#TRPBF
廠商： Linear Technology
文件頁數(shù)： 13/26頁
文件大?。?/td> 311K
描述： IC CNTRLR HOT SWAP 12-DFN
標(biāo)準包裝： 2,500
類型： 熱交換控制器
應(yīng)用： 通用
內(nèi)部開關(guān)： 無
電源電壓： 2.3 V ~ 6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 12-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 12-DFN（4x3）
包裝： 帶卷 (TR)
LTC4216
13
4216fa
For more information www.linear.com/LTC4216
Forexample if C
nF
dV
dt
V ms and
dV
V ms
SS NOM
SS SLOW
,
,
/
.   /   .
(
)
(
)
2   10
1
0 1
=
=
=
After the initial timing cycle, the SS capacitor is charged
by a 10礎(chǔ) current source pull-up and GATE is held low
by the ACL amplifier. As SS ramps up, the ACL amplifier
releases the GATE when it crosses its input offset volt-
age. At this instant, SS switches the pull-up current from
10礎(chǔ) to 1礎(chǔ) for a slower ramp rate. GATE continues to
charge up with 20礎(chǔ) pull-up before the MOSFET reaches
its turn-on threshold voltage. When the external MOSFET
is first turned on, there is always a current step due to the
high gain of the MOSFET. The slower SS ramp rate allows
the gate of the external MOSFET to be turned on with a
smaller inrush current step.
When the external MOSFET is turned on, load current starts
to flow through the sense resistor, developing a voltage
drop across it. This allows the ACL amplifier to servo the
GATE to the voltage across the sense resistor, thus control-
ling the rate of change of the inrush current. At this instant,
SS switches back from 1礎(chǔ) to 10礎(chǔ) current source pull-up
for a normal ramp rate. GATE continues to ramp up as
the ACL amplifier servos to track the SS ramp rate. At the
end of SS ramp-up when SS reaches its final value, GATE
is servoed to 擵
ACL(TH)
 across the sense resistor. If the
voltage across the sense resistor drops below 擵
ACL(TH)
 
due to a falling load current, the ACL amplifier shuts off
and GATE ramps further by a 20礎(chǔ) pull-up.
SS is pulled low under any of the following conditions: in
V
CC
 undervoltage lockout condition, during the first timing
cycle or when the circuit breaker fault times out. If the soft-
start function is not used, leave the SS pin unconnected.
Inrush Control with GATE Capacitor
For applications not requiring soft-start to control the di/dt
of the inrush current during power-up, an alternative way
to limit the inrush is to control the GATE pin voltage slew
rate by connecting an external capacitor, C4, from the GATE
pin to ground, as shown in Figure 7. An external resistor,
R
G
, of 10?prevents high frequency self-oscillations in
the MOSFET. The GATE slew rate is given by:
 
V
dt
A
C
C
GATE
=
?/DIV>
+
20
4
 
(7)
where C
GATE
 is the associated parasitic GATE capacitance
due to the external MOSFETs gate input capacitance, C
ISS
.
The inrush current flowing into the load capacitor, C
LOAD
,
is limited to:
 
I
C
dV
dt
C
C
C
A
INRUSH
LOAD
GATE
LOAD
=
=
+
?/DIV>
"
"
4
20
 (8)
For example, if C
LOAD
 = 4700礔, C4 = 33nF and C
GATE
=
5nF, I
INRUSH
 = 2.5A.
If C
LOAD
 is very large and I
INRUSH
 exceeds the analog
current limit, the GATE is servoed to control the inrush
current to 擵
ACL(TH)
/R
SENSE
.
One limitation with this technique is that it slows down
the system turn-on and turn-off time by adding a capaci-
tor at the GATE pin. Should this technique be used, C4 d
50nF is recommended. However, having an external gate
capacitor helps to eliminate voltage spikes coupled through
the MOSFETs drain-to-gate capacitance to the GATE pin
when the supply power is first applied.
Figure 7. Inrush Control with External Gate Capacitor
SENSEP  SENSEN GATE
FB
C4
**ADDITIONAL DETAILS
  OMITTED FOR CLARITY
LTC4216**
R4
R3
R
SENSE
V
IN
V
OUT
M1
+
C
LOAD
4216 F07
R
G
applicaTions inForMaTion
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