參數(shù)資料
型號(hào)： LTC3880IUJ-1#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： 0.1 A DUAL SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC40
封裝： 6 X 6 MM, LEAD FREE, PLASTIC, WJJD-2, QFN-40
文件頁數(shù)： 29/112頁
文件大?。?/td> 2182K
代理商： LTC3880IUJ-1#PBF
LTC3880/LTC3880-1
23
3880fa
OPERATION
the fault commands. Alternatively, the GPIOn pins can be
used as inputs to detect external faults downstream of
the controller that require an immediate response. The
GPIO0 and/or GPIO1 pins can also be configured as power
good outputs. Power good indicates the controller output
is above the power good threshold. At power-up the pin
will initially be three-state. If it is necessary to have the
desired polarity on the pin at power-up in this configura-
tion, attach a Schottky diode between the RUN pin of the
propagated power good signal and the GPIO pin. The
Cathode must be attached to RUN and the Anode to the
GPIO pin. If the GPIO pin is set to a power good status, the
MFR_GPIO_RESPONSE must be ignore otherwise there
is a latched off condition with the controller.
As described in the Soft-Start section, it is possible to
control start-up through concatenated events. If GPIOn
is used to drive the RUN pin of another controller, the
unfiltered VOUT_UV fault limit should be mapped to the
GPIO pin.
Any fault or warning event will cause the ALERT pin to
assert low. The pin will remain asserted low until the
CLEAR_FAULTS command is issued, the fault bit is written
to a 1 or bias power is cycled or a MFR_RESET command
is issued, or the RUN pins are toggled OFF/ON or the part
is commanded OFF/ON via PMBus or an ARA command
operation is performed. The MFR_GPIO_PROPAGATE_
LTC3880 command determines if the GPIO pins are pulled
low when a fault is detected; however, the ALERT pin is
always pulled low if a fault or warning is detected and the
status bits are updated.
Output and input fault event handling is controlled by the
corresponding fault response byte as specified in Tables 5
to 9. Shutdown recovery from these types of faults can
either be autonomous or latched. For autonomous re-
covery, the faults are not latched, so if the fault condition
is not present after the retry interval has elapsed, a new
soft-start is attempted. If the fault persists, the controller
will continue to retry. The retry interval is specified by the
MFR_RETRY_DELAY command and prevents damage to
the regulator components by repetitive power cycling,
assuming the fault condition itself is not immediately
destructive. The MFR_RETRY_DELAY must be greater
than 120ms. It can not exceed 83.88 seconds.
Channel-to-channel fault dependencies can be created by
connecting GPIOn pins together. In the event of an internal
fault, one or more of the channels is configured to pull
the bussed GPIOn pins low. The other channels are then
configured to shut down when the GPIOn pins are pulled
low. For autonomous group retry, the faulted channel
is configured to let go of the GPIOn pin(s) after a retry
interval, assuming the original fault has cleared. All the
channels in the group then begin a soft-start sequence.
If the fault response is LATCH_OFF, the GPIO pin remains
asserted low until either the RUN pin is toggled OFF/ON
or the part is commanded OFF/ON or the ARA command
operation is performed. The toggling of the RUN either
by the pin or OFF/ON command will clear faults associ-
ated with the channel. If it is desired to have all faults
cleared when either RUN pin is toggled, set bit 0 of MFR_
CONFIG_ALL_LTC3880 to a 1.
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
Additional fault detection and handling capabilities are:
CRC Failure
The integrity of the NVM memory is checked after a power-
onreset.ACRCfailurewillpreventthecontrollerfromleav-
ing the inactive state. If a CRC failure occurs, the CML bit is
set in the STATUS_BYTE and STATUS_WORD commands,
the appropriate bit is set in the STATUS_MFR_SPECIFIC
command, and the ALERT pin will be pulled low. NVM
repair can be attempted by writing the desired configura-
tion to the controller and executing a STORE_USER_ALL
command followed by a CLEAR_FAULTS command.
The LTC3880 manufacturing section of the NVM is mir-
rored. The NVM has the ability to perform limited repair
if either one of the two sections of the manufacturing
section of the NVM configuration becomes corrupted. If
a discrepancy is detected, the “NVM CRC Fault” in the
STATUS_MFR_SPECIFIC command is set. If this bit re-
mains set after being cleared by issuing a CLEAR_FAULTS
or writing a 1 to this bit, an irrecoverable internal fault has
occurred. The user is cautioned to disable both output
powersupplyrailsassociatedwiththisspecificpart.There
are no provisions for field repairing unrecoverable NVM
faults in the manufacturing section.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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