參數(shù)資料
型號: LTC3880EUJ-1#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 0.1 A DUAL SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC40
封裝: 6 X 6 MM, LEAD FREE, PLASTIC, WJJD-2, QFN-40
文件頁數(shù): 50/112頁
文件大小: 2182K
代理商: LTC3880EUJ-1#PBF
LTC3880/LTC3880-1
42
3880fa
APPLICATIONS INFORMATION
TheoptionalSchottkydiodesconductduringthedeadtime
betweentheconductionofthetwopowerMOSFETs.These
preventthebodydiodesofthebottomMOSFETsfromturn-
ing on, storing charge during the dead time and requiring
a reverse recovery period that could cost as much as 3%
in efficiency at high VIN. A 1A to 3A Schottky is generally
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
VARIABLE DELAY TIME, SOFT-START AND OUTPUT
VOLTAGE RAMPING
The LTC3880 must enter the run state prior to soft-start.
The RUN pins are released after the part initializes and VIN
isgreaterthantheVIN_ONthreshold.IfmultipleLTC3880s
are used in an application, they should be configured to
share the same RUN pins. They all hold their respective
RUN pins low until all devices initialize and VIN exceeds
the VIN_ON threshold for all devices. The SHARE_CLK
pin assures all the devices connected to the signal use
the same time base.
After the RUN pin releases, the controller waits for the
user-specified turn-on delay (TON_DELAY) prior to ini-
tiating an output voltage ramp. Multiple LTC3880s and
other LTC parts can be configured to start with variable
delay times. To work correctly, all devices use the same
timing clock (SHARE_CLK) and all devices must share
the RUN pin. This allows the relative delay of all parts to
be synchronized. The actual variation in the delay will be
dependent on the highest clock rate of the devices con-
nected to the SHARE_CLK pin (all Linear Technology ICs
are configured to allow the fastest SHARE_CLK signal to
control the timing of all devices). The SHARE_CLK signal
can be ±10% in frequency, thus the actual time delays will
have some variance.
Soft-start is performed by actively regulating the load volt-
agewhiledigitallyrampingthetargetvoltagefrom0Vtothe
commanded voltage set point. The rise time of the voltage
ramp can be programmed using the TON_RISE command
to minimize inrush currents associated with the start-up
voltage ramp. The soft-start feature is disabled by setting
TON_RISE to any value less than 0.250ms. The LTC3880
will perform the necessary math internally to assure the
voltage ramp is controlled to the desired slope. However,
thevoltageslopecannotbeanyfasterthanthefundamental
limits of the power stage. The shorter TON_RISE time is
set, the more jagged the TON_RISE ramp will appear. The
number of steps in the ramp is equal to TON_RISE/0.1ms.
The LTC3880 PWM will always use discontinuous mode
during the TON_RISE operation. In discontinuous mode,
the bottom gate is turned off as soon as reverse current
is detected in the inductor. This will allow the regulator to
start up into a pre-biased load.
There is no tracking feature in the LTC3880; how-
ever, two outputs can be given the same TON_RISE and
TON_DELAY times to effectively ramp up at the same time.
Because the RUN pins are released at the same time and
both units use the same time base, the outputs will track
very closely. If the circuit is in a PolyPhase configuration,
all timing parameters must be the same.
Thedescribedmethodofstart-upsequencingistimebased.
For concatenated events it is possible to control the RUN
pinbasedontheGPIOpinofadifferentcontroller.TheGPIO
pincanbeconfiguredtoreleasewhentheoutputvoltageof
the converter is greater than the VOUT_UV_FAULT_LIMIT.
It is recommended to use the unfiltered VOUT UV fault limit
because there is little appreciable time delay between the
converter crossing the UV threshold and the GPIO pin
releasing. The unfiltered output can be enabled using the
MFR_GPIO_PROPAGATE_VOUT_UVUFcommand.(Refer
to the MFR section of the PMBus commands in this docu-
ment).Theunfilteredsignalmayhavesomeglitchingasthe
VOUTsignaltransitionsthroughthecomparatorthreshold.
A small internal digital filter of 250s has been added to
minimize this problem. To minimize the risk of GPIO pins
glitching, make the TON_RISE times less than 100ms. If
unwanted transitions still occur on GPIO, place a capacitor
to ground on the GPIO pin to filter the waveform. The RC
time-constant of the filter should be set sufficiently fast to
assure no appreciable delay is incurred. A value of 300s
to 500s will provide some additional filtering without
significantly delaying the trigger event.
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