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參數(shù)資料
| 型號(hào)： | LTC3707IGN-SYNC |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3 A SWITCHING CONTROLLER, 360 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 403K |
| 代理商： | LTC3707IGN-SYNC |
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LTC3707-SYNC
21
3707sfa
corresponds to a frequency of approximately 220kHz. The
nominal operating frequency range of the PLL is 140kHz
to 310kHz.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the ex-
ternal and internal oscillators. This type of phase detector
will not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold-in range,
ΔfH,
is equal to the capture range,
ΔfC:
ΔfH = ΔfC = ±0.5 fO (150kHz-300kHz)
The output of the phase detector is a complementary pair of
current sources charging or discharging the external lter
network on the PLLFLTR pin. A simplied block diagram
is shown in Figure 7.
If the external frequency (fPLLIN)isgreaterthantheoscillator
frequency fOSC, current is sourced continuously, pulling
up the PLLFLTR pin. When the external frequency is less
than fOSC, current is sunk continuously, pulling down the
PLLFLTR pin. If the external and internal frequencies are
the same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. Thus the voltage on the PLLFLTR pin is adjusted
until the phase and frequency of the external and internal
oscillators are identical. At this stable operating point the
phase comparator output is open and the lter capacitor
CLP holds the voltage. The IC PLLIN pin must be driven
from a low impedance source such as a logic gate located
close to the pin. When using multiple LTC3707-SYNC’s
(or LTC1629’s, as shown in Figure 14) for a phase-locked
system, the PLLFLTR pin of the master oscillator should be
biased at a voltage that will guarantee the slave oscillator(s)
ability to lock onto the master’s frequency. A DC voltage
of 0.7V to 1.7V applied to the master oscillator’s PLLFLTR
pin is recommended in order to meet this requirement.
The resultant operating frequency can range from 170kHz
to 270kHz.
The loop lter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The lter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP =10kΩ and CLP is 0.01μF to
0.1μF.
APPLICATIONS INFORMATION
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that
t
V
Vf
ON MIN
OUT
IN
()
<
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the controller is generally less
than 200ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
300ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a signicant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced
on both controllers when the FCB pin drops below 0.8V.
During continuous mode, current ows continuously in
the transformer primary. The secondary winding(s) draw
current only when the bottom, synchronous switch is on.
When primary load currents are low and/or the VIN/VOUT
ratio is low, the synchronous switch may not be on for
a sufcient amount of time to transfer power from the
output capacitor to the secondary load. Forced continuous
operation will support secondary windings providing there
is sufcient synchronous switch duty factor. Thus, the FCB
input pin removes the requirement that power must be
drawn from the inductor primary in order to extract power
from the auxiliary windings. With the loop in continuous
mode, the auxiliary outputs may nominally be loaded
without regard to the primary output load.
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