參數(shù)資料
型號(hào): LTC3445
廠商: Linear Technology Corporation
英文描述: 12-Bit To 24-Bit Multiplexed D-Type Latch With 3-State Outputs 56-SSOP -40 to 85
中文描述: 降壓穩(wěn)壓器的I2C可控雙采用4mm?4mm QFN封裝LDO的
文件頁數(shù): 19/24頁
文件大小: 465K
代理商: LTC3445
19
LTC3445
3445fa
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (
I
LOAD
ESR), where ESR is the effective series
resistance of C
OUT
.
I
LOAD
also begins to charge or
discharge C
OUT
, which generates a feedback error signal.
The regulator loop then acts to return V
OUT
to its steady-
state value. During this recovery time V
OUT
can be moni-
tored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1
μ
F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 C
LOAD
).
Thus, a 10
μ
F capacitor charging to 3.3V would require a
250
μ
s rise time, limiting the charging current to about
130mA.
LDO REGULATORS
The LDOs in the LTC3445 are 50mA low dropout regula-
tors with low quiescent and shutdown currents. Each
device is capable of supplying 50mA at a dropout voltage
of 300mV. The LDOs are current limited to greater than
50mA but less than 75mA. The output voltages of the
LDOs are set with external resistive dividers according to
the following formula:
V
LDOOUT1
= 0.6(1 + R1/R2)
V
LDOOUT2
= 0.6(1 + R3/R4)
(4)
(5)
Output Capacitance and Transient Response
The LTC3445 LDOs are designed to be stable with a wide
range of output capacitors. A minimum output capacitor
of 2.2
μ
F with an ESR of 3
or less is recommended to
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V
CC1
to ground. The resulting
dQ/dt is the current out of V
CC1
that is typically larger
than the DC bias current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V
CC1
and thus
their effects will be more pronounced at higher supply
voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for
less than 2% total additional loss.
APPLICATIU
W
U
U
Figure 8. Power Loss vs Load Current, V
CC1
= 3.6V
LOAD CURRENT (mA)
1
P
10
100
1000
0.1
10
100
1000
3445 F08
0.1
1
DAC MIN
DAC MAX
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