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參數(shù)資料
| 型號： | LTC3445 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 12-Bit To 24-Bit Multiplexed D-Type Latch With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 降壓穩(wěn)壓器的I2C可控雙采用4mm？4mm QFN封裝LDO的 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 465K |
| 代理商： | LTC3445 |
16
LTC3445
3445fa
1
2
C Register Definitions
(POR = 00 for all registers)
REG 0
7
6
5
4
3
2
1
0
REG 1
7
6
5
4
3
2
1
0
0 (Logic Low)
0 (Logic Low)
Buck DAC5
Buck DAC4
Buck DAC3
Buck DAC2
Buck DAC1
Buck DAC0
0 (Logic Low)
0 (Logic Low)
0 (Logic Low)
0 (Logic Low)
0 (Logic Low)
0 (Logic Low)
Slew Rate 1
Slew Rate 0
REG 2
7
6
5
4
3
2
1
0
REG 3
7
6
5
4
3
2
1
0
0 (Logic Low)
0 (Logic Low)
0 (Logic Low)
STATUS—Buck Thermal Shutdown
STATUS—Buck PGOODb
STATUS—LDO2 PGOODb
STATUS—LDO1 PGOODb
Buck Update (GO Bit)
PGOOD Blank Disable
0 (Logic Low)
0 (Logic Low)
0 (Logic Low)
BURST Mode
LDO2 Disable
LDO1 Disable
Buck Disable
OPERATIOU
data line is also left high by the slave and master after a
slave has transmitted a byte of data to the master in a read
operation, but this is a not-acknowledge that indicates that
the data transfer is successful.
(refer to Figure 1)
REG 5
7
6
5
4
3
2
1
0
0 (Logic Low)
% SPR1
% SPR0
(Logic Low)
(Logic Low)
(Logic Low)
(Logic Low)
(Logic Low)
Commands Supported
The LTC3445 supports read byte and write byte com-
mands. For the ACK bits, an S indicates that the slave is
pulling the data line low and an M indicates that the master
is effectively acknowledging by leaving the data line high.
Data Transfer Timing for Write Commands
In order to help assure that bad data is not written into the
part, data from a write command is only stored after a
valid acknowledge has been performed. The part will
detect that SDA is low on the rising edge of SCL that marks
the end of the period in which the LTC3445 acknowledges
the data write and then latch the data during the following
SCL low period.
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