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參數(shù)資料
| 型號： | LTC3445 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 12-Bit To 24-Bit Multiplexed D-Type Latch With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 降壓穩(wěn)壓器的I2C可控雙采用4mm？4mm QFN封裝LDO的 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 465K |
| 代理商： | LTC3445 |
12
LTC3445
3445fa
OPERATIOU
Burst Mode Operation
The LTC3445 is capable of Burst Mode operation, in which
the internal power MOSFETs operate intermittently based
on load demand.
In Burst Mode operation, the peak current of the inductor
is set to approximately 200mA regardless of the output load.
Each burst event can last from a few cycles at light loads
to almost continuous cycling with short sleep intervals at
moderate loads. In between these burst events, the power
MOSFETs and any nonessential circuitry are turned off, re-
ducing the buck regulator’s quiescent current to 6
μ
A. In this
sleep state, the load current is being supplied solely from
the output capacitor. As the output voltage droops, the EA’s
output rises above the sleep threshold, signaling the BURST
comparator to trip and turn the top MOSFET on. This pro-
cess repeats at a rate that is dependent on the load demand.
Short-Circuit Protection
When the output is shorted to ground, the frequency of the
oscillator is reduced to about 300kHz. This frequency
foldback ensures that the inductor current has more time
to decay, thereby preventing current runaway. The
oscillator’s frequency will progressively increase to 1.5MHz
when V
OUT
rises above 0V.
Low Supply Operation
The LTC3445 will operate with input supply voltages as
low as 2.5V, but the maximum allowable output current is
reduced at this low voltage. Figure 3 shows the reduction
in the typical maximum output current as a function of
input voltage for various output voltages.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current sig-
nal at duty cycles in excess of 40%. Normally, this results
in a reduction of maximum inductor peak current for duty
cycles >40%. However, the LTC3445 uses a patent-pend-
ing scheme that counteracts this compensating ramp,
which allows the maximum inductor peak current to re-
main unaffected throughout all duty cycles.
(refer to Figure 1)
V
CC1
(V)
2.5
400
M
600
800
1000
3.5
4.5
3
4
5
3445 F03
1200
1400
500
700
900
1100
1300
5.5
DAC (MIN)
DAC (MAX)
Figure 3. Buck Maximum Peak Current vs V
CC1
Spread Spectrum
The LTC3445 has a spread spectrum mode that can be
enabled via two register bits. In the spread spectrum
mode, the switching frequency is dithered about a center
frequency of 1.5MHz. Spread spectrum lowers noise at the
regulated output and at the input.
Figure 4 shows the noise reduction capabilities of the
LTC3445 in spread spectrum mode. The percent spread of
the frequency is controlled by two bits in register 5.
00 = 0% Spread
01 = 7.4% Spread
10 = 14.8% Spread
11 = 22.4% Spread
DAC
The buck output voltage is controlled by programming a
6-bit DAC register (REG0[5:0]) and GO bit (REG2[0]). The
output voltage range is 0.85V to 1.55V in ~15mV steps.
The DAC setting range is from 0 to 48. Any settings above
48 will default to the 48 settings value. When the desired
DAC setting is loaded, the GO bit needs to be changed from
0 to 1. Once the GO bit transition occurs, V
OUT
will begin
to change to the DAC setting loaded at that instant.
Slew Rate
A 2-bit register is used to control the rate of change of
V
OUT
between DAC settings. The slew rate is controlled
by stepping V
OUT
to its new setting using a series of
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