參數(shù)資料
型號(hào): LTC2428IG
廠(chǎng)商: LINEAR TECHNOLOGY CORP
元件分類(lèi): ADC
英文描述: 4-/8-Channel 20-Bit uPower No Latency ADCs
中文描述: 8-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝: 0.209 INCH, PLASTIC, SSOP-28
文件頁(yè)數(shù): 19/28頁(yè)
文件大?。?/td> 317K
代理商: LTC2428IG
19
LTC2424/LTC2428
APPLICATIO
S I
FOR
ATIO
U
W
U
U
Figure 16. Internal Serial Clock Timing Diagram
SCKCLK
SDO
D
IN
CSADC
CSMUX
t
EOCtest
MSB
LSB
EXR
SIG
BIT0
BIT4 BIT3 BIT2 BIT1
BIT19BIT18
BIT20
BIT21
BIT22
BIT23
24248 F16
TEST EOC
DON’T CARE
DON’T CARE
EN
D2
D1
D0
Hi-Z
Hi-Z
Hi-Z
TEST EOC
TEST EOC
V
CC
CS
10k
F
O
FS
SET
CSMUX
CSADC
SCK
CLK
MUXOUT
ADCIN
GND
D
IN
SDO
ZS
SET
0.1V
TO V
CC
–0.12V
REF
TO 1.12V
REF
CH0
TO CH7
2.7V TO 5.5V
LTC2424/LTC2428
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CSADC remains LOW. In order to prevent the
device from exiting the low power sleep state, CSADC
must be pulled HIGH before the first rising edge of SCK. In
the internal SCK timing mode, SCK goes HIGH and the
device begins outputting data at time t
EOCtest
after the
falling edge of CSADC (if EOC = 0) or t
EOCtest
after EOC
goes LOW (if CSADC is LOW during the falling edge of
EOC). The value of t
EOCtest
is 23
μ
s if the device is using its
internal oscillator (F
0
= logic LOW or HIGH). If F
O
is driven
by an external oscillator of frequency f
EOSC
, then t
EOCtest
is
3.6/f
EOSC
. If CSADC is pulled HIGH before time t
EOCtest
, the
device remains in the sleep state. The conversion result is
held in the internal static shift register.
If CSADC remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 24th
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
While operating in the internal serial clock mode, the SCK
output of the ADC may be used as the multiplexer clock
(CLK). D
IN
is latched into the multiplexer on the rising
edge of CLK. As shown in Figure 16, the multiplexer
channel is selected by serial shifting a 4-bit word into the
D
IN
pin on the rising edge of CLK. The first bit is an enable
bit which must be HIGH in order to program a channel. The
next three bits determine which channel is selected, see
Table 3. On the rising edge of CSADC (falling edge of
CSMUX), the new channel is selected and will be valid for
the next conversion. If D
IN
is held LOW during the data
output state, the previous channel selection remains valid.
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