參數(shù)資料
型號： LTC2428IG
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 4-/8-Channel 20-Bit uPower No Latency ADCs
中文描述： 8-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝： 0.209 INCH, PLASTIC, SSOP-28
文件頁數(shù)： 15/28頁
文件大?。?/td> 317K
代理商： LTC2428IG
15
LTC2424/LTC2428
APPLICATIO
S I
N
FOR
ATIO
U
W
U
Figure 12. Using the LTC2424/LTC2428’s High Accuracy Wide Dynamic Range
to Digitize a 300mV
P-P
15Hz Waveform with a Large DC Offset (V
CC
= 5V, V
REF
= 5V)
1.5
2
2.5
0.5
1
TIME (SEC)
A
2.00
2.05
2.10
24248 F12a
1.95
1.90
1.80
1.85
2.20
2.15
V
IN
= 300mV
P-P
+ 2V DC
25
50
0
FREQUENCY (Hz)
M
–60
–40
–20
0
24248 F12b
–80
–100
–120
15Hz
100sps
2V OFFSET
1.5
2
2.5
1
0.5
TIME (SEC)
A
0.00
0.05
0.10
24248 F12c
–0.05
–0.10
–0.20
–0.15
0.20
0.15
V
IN
= 300mV
P-P
+ 0V DC
25
50
0
FREQUENCY (Hz)
M
–60
–40
–20
0
24248 F12d
–80
–100
–120
15Hz
100sps
0V OFFSET
Figure 12b. FFT Waveform with 2V DC Offset
Figure 12a. Digitized Waveform with 2V DC Offset
Figure 12d. FFT Waveform with No Offset
Figure 12c. Digitized Waveform with No Offset
floating at power-up or during this transition, the converter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.
Multiplexer Serial Input Clock (CLK)
Generally, this pin is externally tied to SCK for 4-wire op-
eration. On the rising edge of CLK (Pin 19) with CSMUX held
HIGH, data is serially shifted into the multiplexer. If CSMUX
is LOW the CLK input will be disabled and the channel
selection unchanged.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 24), drives the serial
data during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CSADC (Pin 23) is HIGH, the SDO driver is switched
to a high impedance state. This allows sharing the serial
interface with other devices. If CSADC is LOW during the
convert or sleep state, SDO will output EOC. If CSADC is
LOW during the conversion phase, the EOC bit appears
HIGH on the SDO pin. Once the conversion is complete,
EOC goes LOW. The device remains in the sleep state until
the first rising edge of SCK occurs while CSADC = 0.
ADC Chip Select Input (CSADC)
The active LOW chip select, CSADC (Pin 23), is used to test
the conversion status and to enable the data output
transfer as described in the previous sections.
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