參數(shù)資料
型號: LTC2428IG
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 4-/8-Channel 20-Bit uPower No Latency ADCs
中文描述: 8-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝: 0.209 INCH, PLASTIC, SSOP-28
文件頁數(shù): 11/28頁
文件大小: 317K
代理商: LTC2428IG
11
LTC2424/LTC2428
Table 3. Logic Table for Channel Selection
CHANNEL STATUS
All Off
CH0
CH1
CH2
CH3
CH4*
CH5*
CH6*
CH7*
*Not used for the LTC2424.
EN
0
1
1
1
1
1
1
1
1
D2
X
0
0
0
0
1
1
1
1
D1
X
0
0
1
1
0
0
1
1
D0
X
0
1
0
1
0
1
0
1
APPLICATIO
S I
N
FOR
ATIO
U
W
U
Frequency Rejection Selection (F
O
Pin Connection)
The LTC2424/LTC2428 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz
±
2% or 60Hz
±
2%. For
60Hz rejection, F
O
(Pin 26) should be connected to GND
(Pin 1) while for 50Hz rejection the F
O
pin should be
connected to V
CC
(Pin2).
The selection of 50Hz or 60Hz rejection can also be made
by driving F
O
to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
Figure 4. Typical Data Input/Output Timing
EOC
“0”
SDO
SCK/CLK
D
IN
CSMUX/CSADC
MSB
LSB
D2
EN
D1
D0
EXT
SIG
BIT 22
BIT 23
BIT 0
24248 F04
Hi-Z
DON’T CARE
t
CONV
Hi-Z
Table 2. LTC2424/LTC2428 Output Data Format
Bit 23
Input Voltage
EOC
V
IN
> 9/8 V
REF
0
9/8 V
REF
0
V
REF
+ 1LSB
0
V
REF
0
3/4V
REF
+ 1LSB
0
3/4V
REF
0
1/2V
REF
+ 1LSB
0
1/2V
REF
0
1/4V
REF
+ 1LSB
0
1/4V
REF
0
0
+
/0
0
–1LSB
0
–1/8 V
REF
0
V
IN
< –1/8 V
REF
0
*The sign bit changes state during the 0 code.
Bit 22
DMY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 21
SIG
1
1
1
1
1
1
1
1
1
1
1/0*
0
0
0
Bit 20
EXR
1
1
1
0
0
0
0
0
0
0
0
1
1
1
Bit 19
MSB
0
0
0
1
1
1
1
0
0
0
0
1
1
1
Bit 18
Bit 17
Bit 16
Bit 15
Bit 0
LSB
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
...
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...
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