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參數(shù)資料
| 型號： | LTC2428C |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State Outputs 56-BGA MICROSTAR JUNIOR -40 to 85 |
| 中文描述： | 4-/8-Channel 20位ADC的無延遲uPower |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 317K |
| 代理商： | LTC2428C |
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20
LTC2424/LTC2428
Figure 17. Internal Serial Clock with Reduced Data Output Length Timing Diagram
SCKCLK
SDO
D
IN
CSADC
CSMUX
t
EOCtest
MSB
EXR
SIG
BIT8
BIT12 BIT11 BIT10 BIT9
BIT19BIT18
BIT20
BIT21
BIT22
BIT23
24248 F17
TEST EOC
DON’T CARE
DON’T CARE
EN
D2
D1
D0
Hi-Z
Hi-Z
Hi-Z
TEST EOC
TEST EOC
V
CC
CS
10k
F
O
FS
SET
CSMUX
CSADC
SCK
CLK
MUXOUT
ADCIN
GND
D
IN
SDO
ZS
SET
0.1V
TO V
CC
–0.12V
REF
TO 1.12V
REF
CH0
TO CH7
2.7V TO 5.5V
LTC2424/LTC2428
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
APPLICATIO
S I
N
FOR
ATIO
U
Typically, CSADC remains LOW during the data output
state. However, the data output state may be aborted by
pulling CSADC HIGH anytime between the first and 24th
rising edge of SCK, see Figure 17. On the rising edge of
CSADC, the device aborts the data output state and
immediately initiates a new conversion. This is useful for
systems not requiring all 24 bits of output data, aborting
an invalid conversion cycle, or synchronizing the start of
a conversion. If CSADC is pulled HIGH while the con-
verter is driving SCK LOW, the internal pull-up is not
available to restore SCK to a logic HIGH state. This will
cause the device to exit the internal serial clock mode on
the next falling edge of CSADC. This can be avoided by
adding an external 10k pull-up resistor to the SCK pin or
by never pulling CSADC HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2424/LTC2428’s internal
pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
W
U
mode. However, certain applications may require an exter-
nal driver on SCK. If this driver goes HI-Z after outputting
a LOW signal, the LTC2424/LTC2428’s internal pull-up
remains disabled. Hence, SCK remains LOW. On the next
falling edge of CSADC, the device is switched to the
external SCK timing mode. By adding an external 10k pull-
up resistor to SCK, this pin goes HIGH once the external
driver goes HI-Z. On the next CSADC falling edge, the
device will remain in the internal SCK timing mode.
A similar situation may occur during the sleep state when
CSADC is pulsed HIGH-LOW-HIGH in order to test the
conversion status. If the device is in the sleep state
(EOC = 0), SCK will go LOW. Once CSADC goes HIGH
(within the time period defined above as t
EOCtest
), the
internal pull-up is activated. For a heavy capacitive load
on the SCK pin, the internal pull-up may not be adequate
to return SCK to a HIGH level before CSADC goes LOW
again. This is not a concern under normal conditions
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| LTC2428CG#TR | 功能描述:IC ADC 20BIT 8CH MICROPWR 28SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
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| LTC2428CGPBF | 制造商:Linear Technology 功能描述:ADC,LTC2428C 20bit D-S 8 ch SPI SSOP |
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