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參數(shù)資料
| 型號： | LTC2308IUF#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 500KSPS 24-QFN |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；8 個單端，雙極；4 個差分，單極；4 個差分，雙極 |
| 配用： | DC1186A-ND - BOARD SAR ADC LTC2308 |
LTC2308
14
2308fb
For best performance, ensure that CONVST returns low
within 40ns after the conversion starts (i.e., before the rst
bit decision) or after the conversion ends. If CONVST is
low when the conversion ends, the MSB bit will appear at
SDO at the end of the conversion and the ADC will remain
powered up.
Timing and Control
The start of a conversion is triggered by a rising edge at
CONVST. Once initiated, a new conversion cannot be re-
started until the current conversion is complete. Figures 8
and 9 show the timing diagrams for two different examples
of CONVST pulses. Example 1 (Figure 8) shows CONVST
staying HIGH after the conversion ends. If CONVST is high
after the tCONV period, the LTC2308 enters NAP or SLEEP
mode, depending on the setting of SLP bit from the DIN
word that was shifted in after the previous conversion.
(see Nap Mode and Sleep Mode for more detail).
When CONVST returns low, the ADC wakes up and the
most signicant bit (MSB) of the output data sequence
at SDO becomes valid after the serial data bus is enabled.
All other data bits from SDO transition on the falling edge
of each SCK pulse. Conguration data (DIN) is loaded into
the LTC2308 at SDI, starting with the rst SCK rising edge
after CONVST returns low. The S/D bit is loaded on the
rst SCK rising edge.
Example 2 (Figure 9) shows CONVST returning low be-
fore the conversion ends. In this mode, the ADC and all
internal circuitry remain powered up. When the conver-
sion is complete, the MSB of the output data sequence at
SDO becomes valid after the data bus is enabled. At this
point(tCONV 1.3μs after the rising edge of CONVST), puls-
ing SCK will shift data out at SDO and load conguration
data (DIN) into the LTC2308 at SDI. The rst SCK rising
edge loads the S/D bit into the LTC2308. SDO transitions
on the falling edge of each SCK pulse.
Figures 10 and 11 are the transfer characteristics for the
bipolar and unipolar modes. Data is output at SDO in 2’s
complement format for bipolar readings and in straight
binary for unipolar readings.
Nap Mode
The ADC enters nap mode when CONVST is held high
after the conversion is complete (tCONV) if the SLP bit is
set to a logic 0. The supply current decreases to 180μA
in nap mode between conversions, thereby reducing the
average power dissipation as the sample rate decreases.
For example, the LTC2308 draws an average of 200μA
with a 1ksps sampling rate. The LTC2308 keeps only the
reference(VREF) and reference buffer(REFCOMP) circuitry
active when in nap mode.
Sleep Mode
The ADC enters sleep mode when CONVST is held high
after the conversion is complete (tCONV) if the SLP bit is
set to a logic 1. The ADC draws only 7μA in sleep mode,
provided that none of the digital inputs are switching. When
CONVST returns low, the LTC2308 is released from the
SLEEP mode and requires 200ms to wake up and charge
the respective 2.2μF and 10μF bypass capacitors on the
VREF and REFCOMP pins.
Board Layout and Bypassing
To obtain the best performance, a printed circuit board with
a solid ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. Care should be taken
not to run any digital signal alongside an analog signal. All
analog inputs should be shielded by GND. VREF, REFCOMP
and AVDD should be bypassed to the ground plane as
close to the pin as possible. Maintaining a low impedance
path for the common return of these bypass capacitors
is essential to the low noise operation of the ADC. These
traces should be as wide as possible. See Figure 7 for a
suggested layout.
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