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參數(shù)資料
| 型號： | LTC2240IUP-12#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 170MSPS 64-QFN |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 170M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 638mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
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LTC2240-12
23
224012fd
APPLICATIONS INFORMATION
some source termination to reduce ringing that may occur
even over a fraction of an inch is advisable. You must not
allow the clock to overshoot the supplies or performance
will suffer. Do not lter the clock signal with a narrow band
lter unless you have a sinusoidal clock source, as the
rise and fall time artifacts present in typical digital clock
signals will be translated into phase noise.
The lowest phase noise oscillators have single-ended si-
nusoidal outputs, and for these devices the use of a lter
close to the ADC may be benecial. This lter should be
close to the ADC to both reduce roundtrip reection times,
as well as reduce the susceptibility of the traces between
the lter and the ADC. If the circuit is sensitive to close-
in phase noise, the power supply for oscillators and any
buffers must be very stable, or propagation delay variation
with supply will translate into phase noise. Even though
these clock sources may be regarded as digital devices,
do not operate them on a digital supply. If your clock is
also used to drive digital devices such as an FPGA, you
should locate the oscillator, and any clock fan-out devices
close to the ADC, and give the routing to the ADC prece-
dence. The clock signals to the FPGA should have series
termination at the driver to prevent high frequency noise
from the FPGA disturbing the substrate of the clock fan-out
device. If you use an FPGA as a programmable divider, you
must re-time the signal using the original oscillator, and
the re-timing ip-op as well as the oscillator should be
close to the ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated in
the waveguides that exist between the layers of multilayer
PCBs. The differential pairs must be close together and
distanced from other signals. The differential pair should
be guarded on both sides with copper distanced at least
3x the distance between the traces, and grounded with
vias no more than 1/4 inch apart.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2240UP-10 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:10-Bit, 170Msps ADC |
| LTC2240UP-12 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 170Msps ADC |
| LTC2241-10 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit 250Msps/ 210Msps/170Msps ADCs |
| LTC2241-12 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 210Msps ADC |
| LTC2241CUP-10 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:10-Bit, 210Msps ADC |
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