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參數(shù)資料
| 型號(hào)： | LTC2240IUP-12#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 14/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 170MSPS 64-QFN |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 170M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 638mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
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LTC2240-12
21
224012fd
APPLICATIONS INFORMATION
Data Format
The LTC2240-12 parallel digital output can be selected
for offset binary or 2’s complement format. The format
is selected with the MODE pin. Connecting MODE to GND
or 1/3VDD selects offset binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 3 shows the logic
states for the MODE pin.
Table 3. MODE Pin Function
MODE PIN
OUTPUT FORMAT
CLOCK DUTY
CYCLE STABILIZER
GND
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overow Bit
An overow output bit indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overow or underow on the
A data bus, while a logic high on the OFB pin indicates an
overow or underow on the B data bus. In LVDS mode,
a differential logic high on the OF+/OF– pins indicates an
overow or underow.
Output Clock
The ADC has a delayed version of the ENC+ input available
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal encode. In
all CMOS modes, A bus data will be updated just after
CLKOUTA rises and can be latched on the falling edge of
CLKOUTA. In demux CMOS mode with interleaved update,
B bus data will be updated just after CLKOUTB rises and
can be latched on the falling edge of CLKOUTB. In demux
CMOS mode with simultaneous update, B bus data will be
updated just after CLKOUTB falls and can be latched on
the rising edge of CLKOUTB. In LVDS mode, data will be
updated just after CLKOUT+/CLKOUT– rises and can be
latched on the falling edge of CLKOUT+/CLKOUT–.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
For example if the converter is driving a DSP powered
by a 1.8V supply then OVDD should be tied to that same
1.8V supply.
Figure 13a. Digital Output Buffer in CMOS Mode
Figure 13b. Digital Output in LVDS Mode
LTC2240-12
224012 F13a
OVDD
VDD
0.1μF
43Ω
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO 2.625V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
LTC2240-12
224012 F13b
OVDD
LVDS
RECEIVER
OGND
1.25V
D
OUT+
0.1μF
2.5V
OUT–
100Ω
+
–
3.5mA
10k
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2240UP-10 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:10-Bit, 170Msps ADC |
| LTC2240UP-12 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 170Msps ADC |
| LTC2241-10 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit 250Msps/ 210Msps/170Msps ADCs |
| LTC2241-12 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 210Msps ADC |
| LTC2241CUP-10 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:10-Bit, 210Msps ADC |
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