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參數(shù)資料
| 型號： | LTC2208CUP-14 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 130Msps ADC |
| 中文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封裝： | 9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大小： | 1056K |
| 代理商： | LTC2208CUP-14 |
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LTC2208-14
22
220814f
The lower limit of the LTC2208-14 sample rate is determined
by droop of the sample and hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
for the LTC2208-14 is 1Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2208-14 can operate in four digital output modes:
standard LVDS, low power LVDS, full rate CMOS, and
demultiplexed CMOS. The LVDS pin selects the mode of
operation. This pin has a four level logic input, centered at
0, 1/3V
DD
, 2/3V
DD
and V
DD
. An external resistor divider can
be used to set the 1/3V
DD
and 2/3V
DD
logic levels. Table 1
shows the logic states for the LVDS pin.
Table 1. LVDS Pin Function
LVDS
0V(GND)
1/3V
DD
2/3V
DD
V
DD
Digital Output Mode
Full-Rate CMOS
Demultiplexed CMOS
Low Power LVDS
LVDS
Digital Output Buffers (CMOS Modes)
Figure 11 shows an equivalent circuit for a single output
buffer in CMOS Mode, Full-Rate or Demultiplexed. Each
buffer is powered by OV
DD
and OGND, isolated from the
ADC power and ground. The additional N-channel transistor
in the output driver allows operation down to low voltages.
The internal resistor in series with the output makes the
output appear as 50
Ω
to external circuitry and eliminates
the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2208-14 should drive a minimum
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as a ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
Figure 10. ENC Drive Using a CMOS to PECL Translator
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2208-14 is 130Msps.
For the ADC to operate properly the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have at
least 3.65ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS. When using a single-ended ENCODE
signal asymmetric rise and fall times can result in duty
cycles that are far from 50%.
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3V
DD
or 2/3V
DD
using external resistors.
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
APPLICATIU
W
U
U
220814 F09
ENC
–
1.6V
V
THRESHOLD
= 1.6V
ENC
+
0.1
μ
F
LTC2208-14
220814 F10
ENC
–
ENC
+
3.3V
3.3V
D0
Q0
Q0
MC100LVELT22
LTC2208-14
83
83
130
130
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| LTC2208IUP-14 | 14-Bit, 130Msps ADC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2208CUP-14#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 130Msps 14-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 14BIT 130MSPS 64-QFN 制造商:Linear Technology 功能描述:IC ADC 14BIT 130MSPS QFN-64 制造商:Linear Technology 功能描述:IC, ADC, 14BIT, 130MSPS, QFN-64; Resolution (Bits):14bit; Sampling Rate:130MSPS; Supply Voltage Type:Single; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Supply Current:401mA; Digital IC Case Style:QFN; No. of Pins:64 ;RoHS Compliant: Yes |
| LTC2208CUP-14#TR | 制造商:Linear Technology 功能描述:IC ADC 14BIT 130MSPS 64-QFN |
| LTC2208CUP-14#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 130Msps 14-bit Parallel/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 14BIT 130MSPS 64-QFN |
| LTC2208CUPPBF | 制造商:Linear Technology 功能描述:ADC 130Msps 16-Bit Parallel/LVDS QFN64EP |
| LTC2208IUP | 制造商:Linear Technology 功能描述:ADC Single Pipelined 130Msps 16-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 130MSPS 64-QFN |
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