參數資料
型號: LTC2208CUP
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 16-Bit, 130Msps ADC
中文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝: 9 X 9 MM, PLASTIC, MO-220-WNJR-5, QFN-64
文件頁數: 1/32頁
文件大?。?/td> 1222K
代理商: LTC2208CUP
LTC2208
1
2208fa
FEATURES
Sample Rate: 130Msps
78dBFS Noise Floor
100dB SFDR
SFDR >83dB at 250MHz (1.5V
P-P
Input Range)
PGA Front End (2.25V
P-P
or 1.5V
P-P
Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
LVDS or CMOS Outputs
Single 3.3V Supply
Power Dissipation: 1.25W
Clock Duty Cycle Stabilizer
Pin Compatible 14-Bit Version
130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit)
64-Pin (9mm
×
9mm) QFN Package
DESCRIPTIO
The LTC
2208 is a 130Msps, sampling 16-bit A/D con-
verter designed for digitizing high frequency, wide dynamic
range signals with input frequencies up to 700MHz. The
input range of the ADC can be optimized with the PGA
front end.
The LTC2208 is perfect for demanding communications
applications, with AC performance that includes 78dBFS
Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultra low jitter of 70fs
RMS
allows undersampling
of high input frequencies with excellent noise performance.
Maximum DC specs include ±4LSB INL, ±1LSB DNL (no
missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC
+
and ENC
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
U
APPLICATIU
TYPICAL APPLICATIO
U
16-Bit, 130Msps ADC
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
64k Point FFT, F
IN
= 15.1MHz,
–1dB, PGA = 0
FREQUENCY (MHz)
0
–130
A
–100
–110
–120
–80
–90
–30
–40
–50
–60
–70
0
–10
–20
10
30
40
20
50
60
2208 G03
+
S/H
AMP
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
16-BIT
PIPELINED
ADC CORE
INTERNAL ADC
REFERENCE
GENERATOR
1.25V
COMMON MODE
BIAS VOLTAGE
CLOCK/DUTY
CYCLE
CONTROL
D15
D0
PGA
SHDN
DITH
MODE
LVDS
RAND
V
CM
ANALOG
INPUT
2208 TA01
CMOS
OR
LVDS
0.5V TO 3.6V
3.3V
3.3V
SENSE
OGND
OV
DD
2.2
μ
F
1
μ
F
1
μ
F
1
μ
F
1
μ
F
V
DD
GND
ADC CONTROL INPUTS
AIN
+
ENC
+
AIN
ENC
OF
CLKOUT
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