參數(shù)資料
型號: LTC2208CUP-14
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 14-Bit, 130Msps ADC
中文描述: 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝: 9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64
文件頁數(shù): 1/28頁
文件大?。?/td> 1056K
代理商: LTC2208CUP-14
LTC2208-14
1
220814f
FEATURES
DESCRIPTIO
The LTC
2208-14 is a 130Msps, sampling 14-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals with input frequencies up to
700MHz. The input range of the ADC can be optimized
with the PGA front end.
The LTC2208-14 is perfect for demanding communications
applications, with AC performance that includes 77.1dBFS
Noise Floor and 98dB spurious free dynamic range (SFDR).
Ultralow jitter of 70fs
RMS
allows undersampling of high
input frequencies with excellent noise performance.
Maximum DC specs include ±1.5LSB INL, ±0.5LSB DNL
(no missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC
+
and ENC
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
U
APPLICATIU
TYPICAL APPLICATIO
U
14-Bit, 130Msps ADC
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
Sample Rate: 130Msps
77.1dBFS Noise Floor
98dB SFDR
SFDR >81dB at 250MHz (1.5V
P-P
Input Range)
PGA Front End (2.25V
P-P
or 1.5V
P-P
Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
LVDS or CMOS Outputs
Single 3.3V Supply
Power Dissipation: 1.32W
Clock Duty Cycle Stabilizer
Pin Compatible 16-Bit Version
130Msps: LTC2208 (16-Bit)
64-Pin (9mm
×
9mm) QFN Package
32k Point FFT, f
IN
= 15.11MHz,
–1dB, PGA = 0, RAND “On”,
Dither “OFF”
+
S/H
AMP
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC CORE
INTERNAL ADC
REFERENCE
GENERATOR
1.25V
COMMON MODE
BIAS VOLTAGE
CLOCK/DUTY
CYCLE
CONTROL
D13
D0
PGA
SHDN
DITH
MODE
LVDS
RAND
V
CM
ANALOG
INPUT
220814 TA01
CMOS
OR
LVDS
0.5V TO 3.6V
3.3V
3.3V
SENSE
OGND
OV
DD
2.2
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
V
DD
GND
ADC CONTROL INPUTS
AIN
+
ENC
+
AIN
ENC
OF
CLKOUT
FREQUENCY (MHz)
0
A
–80
–90
–20
–30
–10
0
20
40
50
220814 G05
–100
–110
–120
–40
–50
–60
–70
10
30
60
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
相關(guān)PDF資料
PDF描述
LTC2208IUP-14 14-Bit, 130Msps ADC
LTC2208UP-14 14-Bit, 130Msps ADC
LTC2208 16-Bit, 130Msps ADC
LTC2208CUP 16-Bit, 130Msps ADC
LTC2208IUP 16-Bit, 130Msps ADC
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