參數(shù)資料
型號: LTC1760
廠商: Linear Technology Corporation
英文描述: Dual Smart Battery System Manager
中文描述: 雙智能電池系統(tǒng)管理
文件頁數(shù): 40/44頁
文件大?。?/td> 379K
代理商: LTC1760
LTC1760
40
sn1760 1760is
APPLICATIOU
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall
times should be minimized. To prevent magnetic and
electrical field radiation and high frequency resonant prob-
lems, proper layout of the components connected to the IC
is essential. (See Figure 11.) Here is a PCB layout priority
list for proper layout. Layout the PCB using this specific
order.
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections. Short-
est copper trace connections possible. These parts must
be on the same layer of copper. Vias must not be used to
make this connection.
W
U
U
1760 F10
V
BAT
L1
V
IN
HIGH
FREQUENCY
CIRCULATING
PATH
BAT
SWITCH NODE
C
IN
C
OUT
D1
Figure 11. High-Speed Switching Path
CSP
1760 F11
DIRECTION OF CHARGING CURRENT
R
SNS
CSN
Figure 12. Kelvin Sensing of Charging Current
2. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for a clean
FET drive. This includes IC supply pins that connect to the
switching FET source pins. The IC can be placed on the
opposite side of the PCB relative to above.
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of this
trace. Make the trace width the minimum amount needed
to support current—no copper fills or pours. Avoid run-
ning the connection using multiple layers in parallel.
Minimize capacitance from this node to any other trace or
plane.
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