參數(shù)資料
型號(hào): LTC1760
廠商: Linear Technology Corporation
英文描述: Dual Smart Battery System Manager
中文描述: 雙智能電池系統(tǒng)管理
文件頁數(shù): 37/44頁
文件大小: 379K
代理商: LTC1760
LTC1760
37
sn1760 1760is
Input and Output Capacitors
In the 4A Lithium Battery Charger (Typical Application
section), the input capacitor (C
IN
) is assumed to absorb all
input switching ripple current in the converter, so it must
have adequate ripple current rating. Worst-case RMS
ripple current will be equal to one half of output charging
current. Actual capacitance value is not critical. Solid
tantalum low ESR capacitors have high ripple current
rating in a relatively small surface mount package, but
caution must be used when tantalum capacitors are used
for input or output bypass High input surge currents can
be created when the adapter is hot-plugged to the charger
or when a battery is connected to the charger. Solid
tantalum capacitors have a known failure mechanism
when subjected to very high turn-on surge currents. Only
Kemet T495 series of “Surge Robust” low ESR tantalums
are rated for high surge conditions such as battery to
ground.
The relatively high ESR of an aluminum electrolytic for
C15, located at the AC adapter input terminal, is helpful in
reducing ringing during the hot-plug event. Refer to AN88
for more information.
Highest possible voltage rating on the capacitor will mini-
mize problems. Consult with the manufacturer before use.
Alternatives include new high capacity ceramic (at least
20
μ
F) from Tokin, United Chemi-Con/Marcon, et al. Other
alternative capacitors include OSCON capacitors from
Sanyo.
The output capacitor (C
OUT
) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:
I
RMS
=
(L1)(f)
V
BAT
V
DCIN
(
)
0.29 (V
BAT
) 1 –
APPLICATIOU
W
U
U
Then the equation to extract C7 is:
C
V
V
T
R
REF
ISET
SET
7
=
= 0.8/0.01/18.77k(10
μ
s)
0.043
μ
F
In order to prevent overshoot during start-up transients
the time constant associated with C7 must be shorter than
the time constant of C5 at the I
TH
pin. If C7 is increased to
improve ripple rejection, then C5 should be increased
proportionally and charger response time to average cur-
rent variation will degrade.
Capacitors C
B1
and C
B2
are used to filter the VDAC delta-
sigma modulation frequency components to a level which
is essentially DC. C
B2
is the primary filter capacitor and
CB1 is used to provide a zero in the response to cancel the
pole associated with C
B2
. Acceptable voltage ripple at V
SET
is about 10mV
P-P
. Since the period of the delta-sigma
switch closure, T
Σ
, is about 11
μ
s and the internal VDAC
resistor, R
VSET
, is 7.2k
, the ripple voltage can be ap-
proximated by:
||
V
V
T
R
C
C
VSET
REF
VSET
B
B
=
)
1
2
Then the equation to extract C
B1
|| C
B2
is:
C
C
V
T
V
R
B
B
REF
VSET
VSET
1
2
||
=
C
B2
should be 10
×
to 20
×
C
B1
to divide the ripple voltage
present at the charger output. Therefore C
B1
= 0.01
μ
F and
C
B2
= 0.1
μ
F are good starting values. In order to prevent
overshoot during start-up transients the time constant
associated with C
B2
must be shorter than the time constant
of C5 at the I
TH
pin. If C
B2
is increased to improve ripple
rejection, then C5 should be increased proportionally and
charger response time to voltage variation will degrade.
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