參數(shù)資料
型號(hào)： LTC1553
廠商： Linear Technology Corporation
英文描述： 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium II Processor(用于奔騰II處理器的5位可編程同步開關(guān)穩(wěn)壓器)
中文描述： 5位可編程同步開關(guān)穩(wěn)壓器控制器的奔騰II處理器（用于奔騰2處理器的5位可編程同步開關(guān)穩(wěn)壓器）
文件頁(yè)數(shù)： 18/24頁(yè)
文件大小： 335K
代理商： LTC1553
18
LTC1553
APPLICATIO
S I
N
FOR
ATIO
U
complication of input and/or output filters, unknown
capacitor ESR, and gross operating point changes with
input voltage, load current variations, all suggest a more
practical empirical method. This can be done by injecting
a transient current at the load and using an RC network box
to iterate toward the final compensation values, or by
obtaining the optimum loop response using a network
analyzer to find the actual loop poles and zeros.
W
U
the suggested values slightly because of board layout and
operating condition differences.
An alternate output capacitor is the Sanyo MV-GX series.
Using multiple parallel 1500
μ
F Sanyo MV-GX capacitors
for the output capacitor, Table 8 shows the suggested
compensation component value for a 5V input application
based on the inductor and output capacitor values.
Table 8. Suggested Compensation Network for 5V Input
Application Using Multiple Paralleled 1500
μ
F SANYO MV-GX
Output Capacitors
L
O
(
μ
H)
1
4500
1
6000
1
9000
2.7
4500
2.7
6000
2.7
9000
5.6
4500
5.6
6000
5.6
9000
C
O
(
μ
F)
R
C
(k
)
4.3
5.6
8.2
11
15
22
24
30
47
C
C
(
μ
F)
0.022
0.0047
0.01
0.01
0.01
0.01
0.01
0.0047
0.0047
C1 (pF)
270
220
150
100
82
56
56
39
27
VID0 to VID4, PWRGD and FAULT
The digital inputs (VID0 to VID4) program the internal DAC
which in turn controls the output voltage. These digital
input controls are intended to be static and are not
designed for high speed switching. Forcing V
OUT
to step
from a high to a low voltage by changing the VID
n
pins
quickly can cause FAULT to trip.
Figure 11 shows the relationship between the V
OUT
volt-
age, PWRGD and FAULT. To prevent PWRGD from inter-
rupting the CPU unnecessarily, the LTC1553 has a built-in
t
PWRBAD
delay to prevent noise at the SENSE pin from
toggling PWRGD. The internal time delay is designed to
take about 500
μ
s for PWRGD to go low and 1ms for it to
recover. Once PWRGD goes low, the internal circuitry
watches for the output voltage to exceed 115% of the rated
voltage. If this happens, FAULT will be triggered. Once
FAULT is triggered, G1 and G2 will be forced low immedi-
ately and the LTC1553 will remain in this state until V
CC
power supply is recycled or OUTEN is toggled.
Table 6. Suggested Compensation Network for 5V Input
Application Using Multiple Paralleled 330
μ
F AVX TPS Output
Capacitors
L
O
(
μ
H)
1
990
1
1980
1
4950
2.7
990
2.7
1980
2.7
4950
5.6
990
5.6
1980
5.6
4950
C
O
(
μ
F)
R
C
(k
)
1.8
3.6
9.1
5.1
10
24
10
20
51
C
C
(
μ
F)
0.022
0.01
0.01
0.01
0.01
0.0047
0.01
0.0047
0.0036
C1 (pF)
680
330
120
220
120
47
120
56
22
Table 7. Suggested Compensation Network for 12V Input
Application Using Multiple Paralleled 330
μ
F AVX TPS Output
Capacitors
L
O
(
μ
H)
1
990
0.82
1
1980
1
4950
2.7
990
2.7
1980
2.7
4950
5.6
990
5.6
1980
5.6
4950
C
O
(
μ
F)
R
C
(k
)
C
C
(
μ
F)
0.047
0.033
0.022
0.033
0.022
0.01
0.022
0.010
0.010
C1 (pF)
1500
820
330
560
270
120
270
150
56
1.5
3.9
2.2
4.3
10
4.3
8.2
22
Tables 6 and 7 show the suggested compensation com-
ponents for 5V and 12V input applications based on the
inductor and output capacitor values. The values were
calculated using multiple paralleled 330
μ
F AVX TPS series
surface mount tantalum capacitors as the output capaci-
tor. The optimum component values might deviate from
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