VIH High Level Input V" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� LTC1289CCN
寤犲晢锛� Linear Technology
鏂囦欢闋佹暩(sh霉)锛� 23/28闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC DATA ACQ SYS 12BIT 3V 20-DIP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 18
椤炲瀷锛� 鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛�
鍒嗚鲸鐜囷紙浣嶏級锛� 12 b
閲囨ǎ鐜囷紙姣忕锛夛細 25k
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶锛屽苟鑱�(li谩n)
闆诲闆绘簮锛� 闆� ±
闆绘簮闆诲锛� ±3.3V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 閫氬瓟
灏佽/澶栨锛� 20-DIP锛�0.300"锛�7.62mm锛�
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 20-PDIP
鍖呰锛� 绠′欢
4
LTC1289
1289fb
LTC1289B
LTC1289C
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
High Level Input Voltage
VCC = 3.6V
鈼�
2.1
V
VIL
Low Level Input Voltage
VCC = 3.0V
鈼�
0.45
V
IIH
High Level Input Current
VIN = VCC
鈼�
2.5
A
IIL
Low Level Input Current
VIN = 0V
鈼�
鈥� 2.5
A
VOH
High Level Output Voltage
VCC = 3.0V
V
IO = 20
A
鈼�
2.90
IO = 400
A
2.7
2.85
VOL
Low Level Output Voltage
VCC = 3.0V
V
IO = 20
A
鈼�
0.05
IO = 400
A
0.10
0.3
IOZ
High Z Output Leakage
VOUT = VCC, CS High
鈼�
3
A
VOUT = 0V, CS High
鈼�
鈥�3
A
ISOURCE
Output Source Current
VOUT = 0V
鈥�10
mA
ISINK
Output Sink Current
VOUT = VCC
9mA
ICC
Positive Supply Current
CS High
鈼�
1.5
5
mA
CS High, Power Shutdown, ACLK Off
鈼�
1.0
10
A
IREF
Reference Current
VREF = 2.5V
鈼�
10
50
A
I鈥�
Negative Supply Current
CS High
鈼�
150
A
ELECTRICAL C
C
HARA TER STICS
DIGITAL A D
U
I
DC
Note 7: Two on-chip diodes are tied to each analog input which will
conduct for analog voltages one diode drop below GND or one diode drop
above VCC. Be careful during testing at low VCC levels, as high level analog
inputs can cause this input diode to conduct, especially at elevated
temperature, and cause errors for inputs near full scale. This spec allows
50mV forward bias of either diode. This means that as long as the analog
input does not exceed the supply voltage by more than 50mV, the output
code will be correct.
Note 8: Channel leakage current is measured after the channel selection.
Note 9: To minimize errors caused by noise at the chip select input, the
internal circuitry waits for two ACLK falling edges after a chip select falling
edge is detected before responding to control input signals. Therefore, no
attempt should be made to clock an address in or data out until the
minimum chip select set-up time has elasped. See Typical Peformance
Characteristics curves for additional information (tsuCS vs VCC).
Note 10: Increased leakage currents at elevated temperatures cause the
S/H to droop, therefore it's recommended that fACLK 鈮� 125kHz at 85掳C and
fACLK 鈮� 15kHz at 25掳C.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND, AGND
and REF 鈥�wired together (unless otherwise noted).
Note 3: VCC = 3V, VREF+ = 2.5V, VREF鈥� = 0V, V 鈥� = 0V for unipolar mode
and 鈥� 3V for bipolar mode, ACLK = 2.0MHz unless otherwise specified.
Note 4: These specs apply for both unipolar and bipolar modes. In bipolar
mode, one LSB is equal to the bipolar input span (2VREF) divided by 4096.
For example, when VREF = 2.5V, 1LSB(bipolar) = 2(2.5)/4096 = 1.22mV.
V 鈥� = 鈥� 2.7V for bipolar mode.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Recommended operating conditions.
The
鈼� denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25掳C. (Note 3)
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
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LTC1289CCSW 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 3V 20-SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡
LTC1289CCSW#PBF 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 3V 20-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡
LTC1289CCSW#TR 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 3V 20SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡
LTC1289CCSW#TRPBF 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 3V 20-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡
鐧�(f膩)甯冪穵鎬ラ噰璩硷紝3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

閲囪臣闇€姹�

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*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣

鎴戠殑鑱�(li谩n)绯绘柟寮�

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