- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗9503 > LTC1289CCN (Linear Technology)IC DATA ACQ SYS 12BIT 3V 20-DIP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | LTC1289CCN |
| 寤犲晢锛� | Linear Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 11/28闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DATA ACQ SYS 12BIT 3V 20-DIP |
| 妯欐簴鍖呰锛� | 18 |
| 椤炲瀷锛� | 鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� |
| 鍒嗚鲸鐜囷紙浣嶏級锛� | 12 b |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 25k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶锛屽苟鑱�(li谩n) |
| 闆诲闆绘簮锛� | 闆� ± |
| 闆绘簮闆诲锛� | ±3.3V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
| 灏佽/澶栨锛� | 20-DIP锛�0.300"锛�7.62mm锛� |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 20-PDIP |
| 鍖呰锛� | 绠′欢 |
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19
LTC1289
1289fb
Figure 14. Reference Input Equivalent Circuit
RON
8pF 鈥� 40pF
LTC1289
REF+
ROUT
VREF
EVERY 4 ACLK CYCLES
14
13
REF鈥�
LTC1289 AIF14
pins on the package ends (DGND and CH0). Grounding
any unused inputs (especially the end pin, CH0) will also
reduce outside coupling into high source resistances.
4. Sample and Hold
Single-Ended Inputs
The LTC1289 provides a built-in sample and hold (S&H)
function for all signals acquired in the single-ended mode
(COM pin grounded). This sample and hold allows the
LTC1289 to convert rapidly varying signals (see typical
curve of S&H Acquisition Time vs Source Resistance). The
input voltage is sampled during the tSMPL time as shown
in Figure 10. The sampling interval begins after the fourth
MUX address bit is shifted in and continues during the
remainder of the data transfer. On the falling edge of the
final SCLK, the S&H goes into hold mode and the conver-
sion begins. The voltage will be held on either the 8th, 12th
or 16th falling edge of the SCLK depending on the word
length selected.
Differential Inputs
With differential inputs or when the COM pin is not tied to
ground, the A/D no longer converts just a single voltage
but rather the difference between two voltages. In these
cases, the voltage on the selected 鈥�+鈥� input is still sampled
and held and therefore may be rapidly time varing just as
in single ended mode. However, the voltage on the se-
lected 鈥溾€撯€� input must remain constant and be free of noise
and ripple throughout the conversion time. Otherwise, the
differencing operation may not be performed accurately.
The conversion time is 52 ACLK cycles. Therefore, a
change in the 鈥溾€撯€� input voltage during this interval can
cause conversion errors. For a sinusoidal voltage on the
鈥溾€撯€� input this error would be:
VERROR (MAX) = VPEAK 脳 2 脳 蟺 脳 f(鈥溾€撯€�) 脳
Where f(鈥溾€撯€�) is the frequency of the 鈥溾€撯€� input voltage,
VPEAK is its peak amplitude and fACLK is the frequency of
the ACLK. In most cases VERROR will not be significant. For
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
a 60Hz signal on the 鈥溾€撯€� input to generate a 1/4LSB error
(150
V) with the converter running at ACLK = 2MHz, its
peak value would have to be 15mV.
5. Reference Inputs
The voltage between the reference inputs of the LTC1289
defines the voltage span of the A/D converter. The refer-
ence inputs will have transient capacitive switching cur-
rents due to the switched capacitor conversion technique
(see Figure 14). During each bit test of the conversion
(every 4 ACLK cycles), a capacitive current spike will be
generated on the reference pins by the A/D. These current
spikes settle quickly and do not cause a problem. How-
ever, if slow settling circuitry is used to drive the reference
inputs, care must be taken to insure that transients caused
by these current spikes settle completely during each bit
test of the conversion.
When driving the reference inputs, two things should be
kept in mind:
1. Transients on the reference inputs caused by the
capacitive switching currents must settle completely
during each bit test (each 4 ACLK cycles). Figures 15
and 16 show examples of both adequate and poor
settling. Using a slower ACLK will allow more time for
the reference to settle. However, even at the maximum
ACLK rate of 2MHz most references and op amps can
be made to settle within the 2
s bit time. For example
an LT1019 used in the shunt mode with a 10
F bypass
capacitor will settle adequately. To minimize power an
LT1004-2.5 can be used with a 10
F bypass capacitor.
For lower value references the LT1004-1.2 with a 1
F
bypass capacitor can be used.
52
fACLK
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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