(408) 432-1900
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� LTC1289CCN
寤犲晢锛� Linear Technology
鏂囦欢闋佹暩(sh霉)锛� 21/28闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC DATA ACQ SYS 12BIT 3V 20-DIP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 18
椤炲瀷锛� 鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛�
鍒嗚鲸鐜囷紙浣嶏級锛� 12 b
閲囨ǎ鐜囷紙姣忕锛夛細 25k
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶锛屽苟鑱�(li谩n)
闆诲闆绘簮锛� 闆� ±
闆绘簮闆诲锛� ±3.3V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 閫氬瓟
灏佽/澶栨锛� 20-DIP锛�0.300"锛�7.62mm锛�
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 20-PDIP
鍖呰锛� 绠′欢
28
LTC1289
1289fb
PACKAGE DESCRIPTIO
U
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 鈼� FAX: (408) 434-0507 鈼� www.linear.com
LINEAR TECHNOLOGY CORPORATION 1992
LT 0506 REV B PRINTED IN USA
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1285/LTC1288
1-/2-Channel, 3V, Micropower 12-Bit ADC
Autoshutdown, SO-8 Package
LTC1290
8-Channel Configurable, 5V, 12-Bit ADC
Pin-Compatible with LTC1289
LTC1391
Serial-Controlled 8-to-1 Analog Multiplexer
Low RON, Low Power, 16-Pin SO and SSOP Package
LTC1401
3V, 12-Bit, 200ksps Serial ADC
15mW, Internal Reference, SO-8 Package
LTC1448
Dual 12-Bit VOUT DACs in SO-8 Package
0.5LBS DNL, 3V to 5V Supply, Swings 0V to VREF
LTC1454/LTC1454L
Dual 12-Bit VOUT DACs in SO-16 Package
5V/3V, Buffered Rail-to-Rail Output, 0.5LSB DNL
LTC1458/LTC1458L
Quad 12-Bit VOUT DACs
5V/3V, Buffered Rail-to-Rail Output, 0.5LSB DNL
LTC1594/LTC1598L
4-/8-Channel, 3V Micropower 12-Bit ADC
Low Power, Small Size
LTC1852/LTC1853
10-Bit/12-Bit, 8-Channel, 400ksps ADCs
3V or 5V, Programmable MUX and Sequencer
LTC2404/LTC2408
24-Bit, 4-/8-Channel, No Latency
危 ADC
4ppm INL, 10ppm Total Unadjusted Error, 200
A
LTC2424/LTC2428
20-Bit, 4-/8-Channel, No Latency
危 ADC
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408
S20 (WIDE) 0502
NOTE 3
.496 鈥� .512
(12.598 鈥� 13.005)
NOTE 4
20
N
19
18
17
16
15
14
13
1
23
4
5
6
78
.394 鈥� .419
(10.007 鈥� 10.643)
910
N/2
11
12
.037 鈥� .045
(0.940 鈥� 1.143)
.004 鈥� .012
(0.102 鈥� 0.305)
.093 鈥� .104
(2.362 鈥� 2.642)
.050
(1.270)
BSC
.014 鈥� .019
(0.356 鈥� 0.482)
TYP
0
掳 鈥� 8掳 TYP
NOTE 3
.009 鈥� .013
(0.229 鈥� 0.330)
.016 鈥� .050
(0.406 鈥� 1.270)
.291 鈥� .299
(7.391 鈥� 7.595)
NOTE 4
脳 45掳
.010 鈥� .029
(0.254 鈥� 0.737)
.420
MIN
.325
卤.005
RECOMMENDED SOLDER PAD LAYOUT
.045
卤.005
N
1
2
3
N/2
.050 BSC
.030
卤.005
TYP
.005
(0.127)
RAD MIN
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SW Package
20-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
LTC1289CCN#PBF 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 3V 20-DIP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡
LTC1289CCSW 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 3V 20-SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡
LTC1289CCSW#PBF 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 3V 20-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡
LTC1289CCSW#TR 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 3V 20SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡
LTC1289CCSW#TRPBF 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 3V 20-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡