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參數(shù)資料
| 型號(hào)： | LT1715CMS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 4ns, 150MHz Dual Comparator with Independent Input/Output Supplies |
| 中文描述： | DUAL COMPARATOR, 3500 uV OFFSET-MAX, PDSO10 |
| 封裝： | PLASTIC, MSOP-10 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大小： | 239K |
| 代理商： | LT1715CMS |
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LT1715
The level translator designs assume one gate load. Mul-
tiple gates can have significant I
IH
loading, and the trans-
mission line routing and termination issues also make this
case difficult.
ECL, and particularly PECL, is valuable technology for
high speed system design, but it must be used with care.
With less than a volt of swing, the noise margins need to
be evaluated carefully. Note that there is some degrada-
tion of noise margin due to the
±
5% resistor selections
shown. With 10KH/E, there is no temperature compensa-
tion of the logic levels, whereas the LT1715 and the
circuits shown give levels that are stable with tempera-
ture. This will lower the noise margin over temperature.
In some configurations it is possible to add compensation
with diode or transistor junctions in series with the
resistors of these networks.
For more information on ECL design, refer to the ECLiPS
data book (DL140), the 10KH system design handbook
(HB205) and PECL design (AN1406), all from Motorola,
now ON Semiconductor.
Circuit Description
The block diagram of the LT1715 is shown in Figure 9. The
circuit topology consists of a differential input stage, a
gain stage with hysteresis and a complementary com-
mon-emitter output stage. All of the internal signal paths
utilize low voltage swings for high speed at low power.
The input stage topology maximizes the input dynamic
range available without requiring the power, complexity
and die area of two complete input stages such as are
found in rail-to-rail input comparators. With a single 2.7V
supply, the LT1715 still has a respectable 1.6V of input
common mode range. The differential input voltage range
is rail-to-rail, without the large input currents found in
competing devices. The input stage also features phase
reversal protection to prevent false outputs when the
inputs are driven below the –100mV common mode
voltage limit.
The internal hysteresis is implemented by positive, nonlin-
ear feedback around a second gain stage. Until this point,
the signal path has been entirely differential. The signal
path is then split into two drive signals for the upper and
lower output transistors. The output transistors are con-
nected common emitter for rail-to-rail output operation.
The Schottky clamps limit the output voltages at about
300mV from the rail, not quite the 50mV or 15mV of Linear
Technology’s rail-to-rail amplifiers and other products.
But the output of a comparator is digital, and this output
stage can drive TTL or CMOS directly. It can also drive ECL,
as described earlier, or analog loads.
The bias conditions and signal swings in the output stage
are designed to turn their respective output transistors off
faster than on. This helps minimize the surge of current
from +V
S
to ground that occurs at transitions, to minimize
APPLICATIOU
W
U
U
Figure 9. LT1715 Block Diagram
–
+
–
+
–
+
–
+
+IN
–IN
A
V1
V
CC
V
EE
A
V2
NONLINEAR STAGE
OUT
GND
1715 F09
+V
S
+
Σ
+
Σ
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| LT1761-1.8 | 100mA, Low Noise, LDO Micropower Regulators in SOT-23(1.8V輸出，100mA,低噪聲，低壓差穩(wěn)壓器（SOT-23封裝）) |
| LT1761-2 | 100mA, Low Noise, LDO Micropower Regulators in SOT-23(2V輸出，100mA,低噪聲，低壓差穩(wěn)壓器（SOT-23封裝）) |
| LT1761-2.5 | 100mA, Low Noise, LDO Micropower Regulators in SOT-23(2.5V輸出，100mA,低噪聲，低壓差穩(wěn)壓器（SOT-23封裝）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LT1715CMS#PBF | 功能描述:IC COMPARATOR 150MHZ DUAL 10MSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 比較器 系列:UltraFast™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類(lèi)型:帶電壓基準(zhǔn) 元件數(shù):4 輸出類(lèi)型:開(kāi)路漏極 電壓 - 電源，單路/雙路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標(biāo)準(zhǔn)）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:- 磁滯:- 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 安裝類(lèi)型:表面貼裝 包裝:管件 產(chǎn)品目錄頁(yè)面:1386 (CN2011-ZH PDF) |
| LT1715CMS#PBF | 制造商:Linear Technology 功能描述:High Speed Comparator IC |
| LT1715CMS#PBF | 制造商:Linear Technology 功能描述:IC HIGH SPEED COMPARATOR |
| LT1715CMS#TR | 功能描述:IC COMPARATOR 150MHZ DUAL 10MSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 線性 - 比較器 系列:UltraFast™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:通用 元件數(shù):1 輸出類(lèi)型:CMOS，推挽式，滿(mǎn)擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類(lèi)型:表面貼裝 包裝:管件 其它名稱(chēng):Q3554586 |
| LT1715CMS#TRPBF | 功能描述:IC COMPARATOR 150MHZ DUAL 10MSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 比較器 系列:UltraFast™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:通用 元件數(shù):1 輸出類(lèi)型:CMOS，推挽式，滿(mǎn)擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類(lèi)型:表面貼裝 包裝:管件 其它名稱(chēng):Q3554586 |
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