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| 型號(hào)： | LT1680ISW#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 200 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.300 INCH, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 217K |
| 代理商： | LT1680ISW#TRPBF |
13
LT1680
Power MOSFET and Output Rectifying Diode Selection
LT1680 converter system parameters that dictate selec-
tion criteria for the switch MOSFET and output rectifying
diode include maximum load current (IOUT), inductor
average current (IAVG) and inductor ripple current (I),
and maximum input and output voltages.
The switch MOSFETs selected must have a maximum
operating VDSS exceeding the maximum output voltage
(VOUT). VGS rated operating maximums must exceed the
12VIN supply voltage. Once voltage requirements have
been determined, switch conduction resistance (RDS(ON))
can be determined based on allowable power dissipation.
In a typical LT1680 boost converter, the switch current is
equal to the inductor current, but is chopped according to
duty cycle (DC). The conduction loss (PLOSS) for a given
FET RDS(ON) can be calculated using the relation:
PLOSS ≈ (DC)(RDS(ON))(IAVG2 + [I2/12])
where IAVG = average inductor current and I = peak-to-
peak inductor ripple current.
The output diode is often a major source of power loss in
switching regulators and selection of adequately rated
diodes is important. In a boost converter, when the output
voltage is significantly higher than the input voltage, the
peak diode current becomes much higher than average
imposes an exponential increase in the slope compensa-
tion waveform, further increasing the effective compen-
sation slope up to 20% for a given setting.
Design example:
VIN = 20V
VOUT = 80V (DC = 0.75)
RSENSE = 0.01
fO = 100kHz
L = 20
H
The minimum inductor usable with no additional slope
compensation is:
L
V
H
MIN ≥
()
()(
)
()(
)(
)
=
20
0 01
1 5 1
0 084 100000 1 0 75
47 6
.. –
.– .
.
Since L = 20
H is less than LMIN, additional slope
compensation is necessary. The total slope compensa-
tion required is:
S
V
H
X ≥
()
=
20
15 1
10 75
2106
.–
–.
()(
)
Amp/s
Subtracting the internally generated slope compensation
and solving for the required effective resistance at SL/ADJ
yields:
R
f
Rf
k
EQ
O
SENSE
O
≤
()( )
()
()() ( )( )
=
2500
2 10
0 084
21 5
6
–.
.
Setting the resistor divider reference voltage to 2V assures
that the additional compensation waveform will be en-
abled at a 75% duty cycle. As shown in Figure 7a, using
RSL1 = 45k and RSL2 = 30k sets the desired reference
voltage and has a RTH of 18k, which meets both design
requirements. Figure 7b shows the slope compensation
effective waveforms both with and without the SL/ADJ
external resistors.
Figure 7a. External Slope Compensation Resistors
16
1
RSL1
45k
RSL2
30k
1680 F07a
5VREF
SL/ADJ
LT1680
(0.084 + 0.139)(fO)
RSENSE
(0.084)(fO)
RSENSE
2.5V
2V
0.8V
DC = 0.75
1680 F07b
Figure 7b. Slope Compensation Waveforms
APPLICATIO S I FOR ATIO
WU
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